RISC-V: Fix PLIC pending bitfield reads
authorMichael Clark <mjc@sifive.com>
Fri, 14 Dec 2018 00:18:54 +0000 (00:18 +0000)
committerPalmer Dabbelt <palmer@sifive.com>
Thu, 20 Dec 2018 20:08:43 +0000 (12:08 -0800)
commite41848e5c9245947c09fb0cf3e160ec9350907f4
treee3013e1c229a2d25f835861141232efea0e6971d
parentef9e41df680a494dec92fe8d166cb2bc531b29a4
RISC-V: Fix PLIC pending bitfield reads

The address calculation for the pending bitfield had
a copy paste bug. This bug went unnoticed because the Linux
PLIC driver does not read the pending bitfield, rather it
reads pending interrupt numbers from the claim register
and writes acknowledgements back to the claim register.

Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Reported-by: Vincent Siles <vincent.siles@ens-lyon.org>
Signed-off-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
hw/riscv/sifive_plic.c