drm/i915/dpio: Fix VLV DPIO PLL register dword numbering
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 22 Apr 2024 08:34:47 +0000 (11:34 +0300)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Tue, 30 Apr 2024 18:08:12 +0000 (21:08 +0300)
commite55f8dfa35ba9ffa344ebd47b65c5be2a4ee6675
tree60035b86cfbc9bce3bb915633232a923a5cdd479
parenta39eec19753be43de10fd251191a3f9fc65dd8d1
drm/i915/dpio: Fix VLV DPIO PLL register dword numbering

The spreadsheet defines the PLL register block as having
the dwords in the following order:

block   dwords    offsets
PLL1    0x0-0x7   0x00-0x1f
PLL2    0x0-0x7   0x20-0x3f
PLL1ext 0x10-0x1f 0x40-0x5f
PLL2ext 0x10-0x1f 0x60-0x7f

So dword indexes 0x8-0xf don't even exist. Renumber
our register defines to match.

Note that the spreadsheet used hex numbering whereas our
defiens are in decimal. Perhaps we should change that?

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240422083457.23815-5-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/display/intel_dpll.c
drivers/gpu/drm/i915/i915_reg.h