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(parent: bb72692) | patch
SiFive RISC-V PRCI Block
authorMichael Clark <mjc@sifive.com>
Fri, 2 Mar 2018 12:31:14 +0000 (01:31 +1300)
committerMichael Clark <mjc@sifive.com>
Tue, 6 Mar 2018 19:30:28 +0000 (08:30 +1300)
commite6b8552c655aad405e7dc28d84b4a6d5324f1b92
tree5532b74c8d05909e1579b6cbbf815e1784f42a7atree | snapshot
parentbb72692cbdbeeef88f4dd1828c1ad6f92cd57b7ecommit | diff
SiFive RISC-V PRCI Block

Simple model of the PRCI  (Power, Reset, Clock, Interrupt) to emulate
register reads made by the SDK BSP.

Acked-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
hw/riscv/sifive_prci.c [new file with mode: 0644] blob
include/hw/riscv/sifive_prci.h [new file with mode: 0644] blob
Unnamed repository; edit this file 'description' to name the repository.