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(parent: 7d47ac9) | patch
target/arm: Implement SVE2 XAR
authorRichard Henderson <richard.henderson@linaro.org>
Tue, 25 May 2021 01:03:09 +0000 (18:03 -0700)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 25 May 2021 15:01:44 +0000 (16:01 +0100)
commite6eba6e532a5f19519d925c8f68da032537abcac
tree1b948454d2264b3ee6594809241084480753ef98tree | snapshot
parent7d47ac94a7c15e820d41adda4cf706c2001e675ccommit | diff
target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
target/arm/helper-sve.h diff | blob | history
target/arm/helper.h diff | blob | history
target/arm/sve.decode diff | blob | history
target/arm/sve_helper.c diff | blob | history
target/arm/translate-a64.c diff | blob | history
target/arm/translate-a64.h diff | blob | history
target/arm/translate-sve.c diff | blob | history
target/arm/vec_helper.c diff | blob | history
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