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target/loongarch: Support LoongArch32 TLB entry
authorJiajie Chen <c@jia.je>
Tue, 22 Aug 2023 07:13:47 +0000 (09:13 +0200)
committerSong Gao <gaosong@loongson.cn>
Thu, 24 Aug 2023 03:17:56 +0000 (11:17 +0800)
commite70bb6fb9afd0c560b3200b569d9d47239448c30
treecc15da1ff9d3999a482621cd4c013889f91242c3tree | snapshot
parentebda3036e18b84d3e4280f05ac71ad462593e8accommit | diff
target/loongarch: Support LoongArch32 TLB entry

The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.

Signed-off-by: Jiajie Chen <c@jia.je>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Song Gao <gaosong@loongson.cn>
Message-ID: <20230822032724.1353391-2-gaosong@loongson.cn>
Message-Id: <20230822071405.35386-2-philmd@linaro.org>
target/loongarch/cpu-csr.h diff | blob | history
target/loongarch/tlb_helper.c diff | blob | history
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