target/riscv: Add support for Zve64x extension
authorJason Chien <jason.chien@sifive.com>
Thu, 28 Mar 2024 02:23:11 +0000 (10:23 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 3 Jun 2024 01:12:12 +0000 (11:12 +1000)
commite7dc5e160f69678432c24827b522baf82b73688a
treef50cfaf28f97f131aebaa3e62a3d0b46a53dacb8
parent9fb41a4418efb6008bce218d9510db830fd744ab
target/riscv: Add support for Zve64x extension

Add support for Zve64x extension. Enabling Zve64f enables Zve64x and
enabling Zve64x enables Zve32x according to their dependency.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2107
Signed-off-by: Jason Chien <jason.chien@sifive.com>
Reviewed-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240328022343.6871-3-jason.chien@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.c
target/riscv/cpu_cfg.h
target/riscv/tcg/tcg-cpu.c