target/riscv: Add counter delegation definitions
authorKaiwen Xue <kaiwenx@rivosinc.com>
Fri, 10 Jan 2025 08:21:34 +0000 (00:21 -0800)
committerAlistair Francis <alistair.francis@wdc.com>
Sat, 18 Jan 2025 23:44:35 +0000 (09:44 +1000)
commite84af935607e3df409cbf0854bc4f4a1b828ce76
tree072e8bf6e5a9e99ad76caf6d740dbeae8af8a824
parentf2548886b3dff228b82e91808553616c4b8d14a8
target/riscv: Add counter delegation definitions

This adds definitions for counter delegation, including the new
scountinhibit register and the mstateen.CD bit.

Signed-off-by: Kaiwen Xue <kaiwenx@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Message-ID: <20250110-counter_delegation-v5-6-e83d797ae294@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu.h
target/riscv/cpu_bits.h
target/riscv/machine.c