drm/xe: Drop GFX_FLSH_CNTL_GEN6 write during GGTT invalidation
authorMatt Roper <matthew.d.roper@intel.com>
Tue, 18 Apr 2023 23:02:47 +0000 (16:02 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:31:42 +0000 (18:31 -0500)
commite881b1292f1791826476f1a2eaf80cc85e2677c5
tree5d8e4b6f9307b53af7c3f58f7bc5ef03ce67b92c
parentd33dc1dc29cab7871f9b0adee7b94b4dc5de5cb1
drm/xe: Drop GFX_FLSH_CNTL_GEN6 write during GGTT invalidation

The write of GFX_FLSH_CNTL_GEN6 was inherited from the i915 codebase
where it was used to force a flush of the write-combine buffer in cases
where the GSM/GGTT were mapped as WC.  Since Xe never uses WC mappings
of the GGTT, this register write is unnecessary.  Furthermore, this
register was removed on Xe_HP-based platforms, so this write winds up
clobbering an unrelated register.

v2:
 - Also drop GFX_FLSH_CNTL_GEN6 from the register file now that it's no
   longer used.  (Lucas)

Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230418230247.3802438-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_ggtt.c