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(parent: f18e314) | patch
ARM: OMAP5: Make L4SEC clock domain SWSUP only
authorTero Kristo <t-kristo@ti.com>
Wed, 29 Apr 2020 14:30:02 +0000 (17:30 +0300)
committerTony Lindgren <tony@atomide.com>
Tue, 5 May 2020 18:16:06 +0000 (11:16 -0700)
commite88ba436e5615f5bb94deecbbb924227b15bbebb
tree3c8d5b8cd4c9cf711b2be87b38d1e8a99fb6ec2ctree | snapshot
parentf18e314a6bf1b7bdbc6f5af1d6dbda11bc2dd35bcommit | diff
ARM: OMAP5: Make L4SEC clock domain SWSUP only

Commit c2ce5fb3f3f5 ('ARM: OMAP: DRA7xx: Make L4SEC clock domain SWSUP
only') made DRA7 SoC L4SEC clock domain SWSUP only because of power
state transition issues detected with HWSUP mode. Based on
experimentation similar issue exists on OMAP5, so do the same change
for OMAP5 also.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
arch/arm/mach-omap2/clockdomains54xx_data.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git