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(parent: 6ac269c) | patch
tests/tcg/xtensa: update test_fp0_arith for DFPU
authorMax Filippov <jcmvbkbc@gmail.com>
Tue, 30 Jun 2020 21:52:25 +0000 (14:52 -0700)
committerMax Filippov <jcmvbkbc@gmail.com>
Fri, 21 Aug 2020 19:48:15 +0000 (12:48 -0700)
commite95ef43181b49a401d163729d0d96f304525dfe7
tree17b1eec6333d72b90f255cc3f2ba9c4b86349421tree | snapshot
parent6ac269c33cd50679ed37b0bafcef0a95b76b1543commit | diff
tests/tcg/xtensa: update test_fp0_arith for DFPU

DFPU arithmetic opcodes update FSR flags. Add FSR parameters and
expected FSR register values for the arithmetic tests.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
tests/tcg/xtensa/fpu.h [new file with mode: 0644] blob
tests/tcg/xtensa/test_fp0_arith.S diff | blob | history
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