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(parent: 61c44bc) | patch
hw/cxl: Support 4 HDM decoders at all levels of topology
authorJonathan Cameron <Jonathan.Cameron@huawei.com>
Wed, 13 Sep 2023 13:25:23 +0000 (14:25 +0100)
committerMichael S. Tsirkin <mst@redhat.com>
Wed, 4 Oct 2023 22:15:06 +0000 (18:15 -0400)
commite967413fe0f2f3fe022658bb279aef95d24210ec
tree3eb67a2a6c57b3cd54284811570bd2b38ec1cbf8tree | snapshot
parent61c44bcf510f4db51c28d0288e528cfdf0ebabc3commit | diff
hw/cxl: Support 4 HDM decoders at all levels of topology

Support these decoders in CXL host bridges (pxb-cxl), CXL Switch USP
and CXL Type 3 end points.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Message-Id: <20230913132523.29780-5-Jonathan.Cameron@huawei.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
hw/cxl/cxl-component-utils.c diff | blob | history
hw/cxl/cxl-host.c diff | blob | history
hw/mem/cxl_type3.c diff | blob | history
include/hw/cxl/cxl_component.h diff | blob | history
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