i2c: npcm: Correct register access width
authorTyrone Ting <kfting@nuvoton.com>
Tue, 17 May 2022 10:11:38 +0000 (18:11 +0800)
committerWolfram Sang <wsa@kernel.org>
Sat, 21 May 2022 05:52:56 +0000 (07:52 +0200)
commitea9f8426d17620214ee345ffb77ee6cc196ff14f
tree8fa1ad7247975d96d0c5c4805db9ef2f5a6b88c7
parent0bf58eb12f05e2f2ae693977206fef868d9c5dce
i2c: npcm: Correct register access width

The SMBnCTL3 register is 8-bit wide and the 32-bit access was always
incorrect, but simply didn't cause a visible error on the 32-bit machine.

On the 64-bit machine, the kernel message reports that ESR value is
0x96000021. Checking Arm Architecture Reference Manual Armv8 suggests that
it's the alignment fault.

SMBnCTL3's address is 0xE.

Fixes: 56a1485b102e ("i2c: npcm7xx: Add Nuvoton NPCM I2C controller driver")
Signed-off-by: Tyrone Ting <kfting@nuvoton.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Signed-off-by: Wolfram Sang <wsa@kernel.org>
drivers/i2c/busses/i2c-npcm7xx.c