mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase
authorDinh Nguyen <dinguyen@kernel.org>
Mon, 14 Nov 2022 23:02:15 +0000 (17:02 -0600)
committerUlf Hansson <ulf.hansson@linaro.org>
Wed, 7 Dec 2022 12:22:37 +0000 (13:22 +0100)
commitef87bd81cb881377c1eaf512167b0522c825b012
tree47be039c443d7dbfb8363dfbc1efd3d8e56f3d19
parentccfa2466a456f70c0bab0cd0b64d6c8996141d2e
mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase

The clock-phase settings for the SDMMC controller in the SoCFPGA
platforms reside in a register in the System Manager. Add a method
to access that register through the syscon interface.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lore.kernel.org/r/20221114230217.202634-4-dinguyen@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
drivers/mmc/host/dw_mmc-pltfm.c