target/riscv: rvv: Provide a fast path using direct access to host ram for unit-strid...
authorMax Chou <max.chou@sifive.com>
Wed, 18 Sep 2024 17:14:10 +0000 (01:14 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Thu, 7 Nov 2024 02:32:10 +0000 (12:32 +1000)
commitf00089267df8d6c9b8c8cc92aa0ba22737f6dfd2
tree32d0fc11603aa944a896af88439d8a230e7baefe
parent3333000f693e31fd9c5bf3e50f21c90b8ca1b512
target/riscv: rvv: Provide a fast path using direct access to host ram for unit-stride load-only-first load instructions

The unmasked unit-stride fault-only-first load instructions are similar
to the unmasked unit-stride load/store instructions that is suitable to
be optimized by using a direct access to host ram fast path.

Signed-off-by: Max Chou <max.chou@sifive.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-ID: <20240918171412.150107-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/vector_helper.c