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(parent: 428a575) | patch
arm64: dts: hi3798cv200: add GICH, GICV register space and irq
authorYang Xiwen <forbidden405@outlook.com>
Mon, 19 Feb 2024 15:05:27 +0000 (23:05 +0800)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Mon, 8 Apr 2024 07:29:33 +0000 (09:29 +0200)
commitf00a6b9644a5668e25ad9ca5aff53b6de4b0aaf6
tree5dc5d2c626fee9f664c804c61249b159c8aac86etree | snapshot
parent428a575dc9038846ad259466d5ba109858c0a023commit | diff
arm64: dts: hi3798cv200: add GICH, GICV register space and irq

This is needed by KVM to make use of VGIC code. Just like regular
GIC-400, PPI #9 is the hypervisor maintenance interrupt. It has been
verified.

Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240219-cache-v3-2-a33c57534ae9@outlook.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git