projects / linux.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: c6b1737) | patch
arm64: dts: renesas: r8a779g0: Add L3 cache controller
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 14 Nov 2022 12:49:00 +0000 (13:49 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Thu, 17 Nov 2022 19:25:35 +0000 (20:25 +0100)
commitf08407210db921a4c9eaeaa92d0c434858b9c6c4
tree7b209e523ac57cec93a1fd5800c78cd001adf4aftree | snapshot
parentc6b1737f45ca708fee76a30afb4a7b0247455749commit | diff
arm64: dts: renesas: r8a779g0: Add L3 cache controller

Describe the cache configuration for the first Cortex-A76 CPU core on
the Renesas R-Car V4H (R8A779G0) SoC.

Extracted from a larger patch in the BSP by Takeshi Kihara.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/dfd743b32198295afb78bc0ac337ef283fa3879a.1668429870.git.geert+renesas@glider.be
arch/arm64/boot/dts/renesas/r8a779g0.dtsi diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git