target/mips: Add missing default cases for some nanoMIPS pools
authorStefan Pejic <stefan.pejic@syrmia.com>
Wed, 4 May 2022 11:04:02 +0000 (13:04 +0200)
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>
Sat, 11 Jun 2022 09:36:01 +0000 (11:36 +0200)
commitf1663114dfb452acd2abd6585f66779ef6a84010
tree6eac52adb373c177e6454798abfad1dd87c1e2db
parentdb7596989a67a8f838416f687431f3a0ccb181a0
target/mips: Add missing default cases for some nanoMIPS pools

Switch statements for the code segments that handle nanoMIPS
instruction pools P.LL, P.SC, P.SHIFT, P.LS.S1, P.LS.E0, PP.LSXS
do not have proper default case, resulting in not generating
reserved instruction exception for certain illegal opcodes.

Fix this by adding default cases for these switch statements that
trigger reserved instruction exception.

Signed-off-by: Stefan Pejic <stefan.pejic@syrmia.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20220504110403.613168-7-stefan.pejic@syrmia.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
target/mips/tcg/nanomips_translate.c.inc