drm/msm: Don't break exclusive fence ordering
authorDaniel Vetter <daniel.vetter@ffwll.ch>
Thu, 5 Aug 2021 10:47:01 +0000 (12:47 +0200)
committerDaniel Vetter <daniel.vetter@ffwll.ch>
Mon, 30 Aug 2021 09:02:14 +0000 (11:02 +0200)
commitf1b3f696a084534a87619ac1a6aa81e78bf86437
tree33f4cec6a70be400345565470450a7158cc1c217
parent80bcfbd3766881930e9a731367da14fd763e9086
drm/msm: Don't break exclusive fence ordering

There's only one exclusive slot, and we must not break the ordering.

Adding a new exclusive fence drops all previous fences from the
dma_resv. To avoid violating the signalling order we err on the side of
over-synchronizing by waiting for the existing fences, even if
userspace asked us to ignore them.

A better fix would be to us a dma_fence_chain or _array like e.g.
amdgpu now uses, but
- msm has a synchronous dma_fence_wait for anything from another
  context, so doesn't seem to care much,
- and it probably makes sense to lift this into dma-resv.c code as a
  proper concept, so that drivers don't have to hack up their own
  solution each on their own.

v2: Improve commit message per Lucas' suggestion.

Cc: Lucas Stach <l.stach@pengutronix.de>
Acked-by: Rob Clark <robdclark@gmail.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Cc: Rob Clark <robdclark@gmail.com>
Cc: Sean Paul <sean@poorly.run>
Cc: linux-arm-msm@vger.kernel.org
Cc: freedreno@lists.freedesktop.org
Link: https://patchwork.freedesktop.org/patch/msgid/20210805104705.862416-17-daniel.vetter@ffwll.ch
drivers/gpu/drm/msm/msm_gem_submit.c