drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables
authorVille Syrjälä <ville.syrjala@linux.intel.com>
Mon, 11 Dec 2023 22:17:59 +0000 (00:17 +0200)
committerVille Syrjälä <ville.syrjala@linux.intel.com>
Wed, 13 Dec 2023 18:49:40 +0000 (20:49 +0200)
commitf23fe4d7d794c6d71dc6b8fdc510da2fc2174369
tree65429557e10a6ecf5c6bb4b93f9fec5b7749c2f5
parente1a914aef28f39aec5f107f31478d95aff3ae6db
drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables

The cdclk->voltage_level if ladders are hard to read, especially as
they're written the other way around compared to how bspec lists
the limits. Let's rewrite them to use simple arrays that gives us
the max cdclk for each voltage level.

v2: Bump the jsl/ehl max cdclk in the table to 652.8 MHz to
    accommodate JSL machines in CI that boot with high cdclk

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231211221759.29725-1-ville.syrjala@linux.intel.com
drivers/gpu/drm/i915/display/intel_cdclk.c