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(parent: 5a2ae23) | patch
target/riscv: Enable uxl field write
authorLIU Zhiwei <zhiwei_liu@c-sky.com>
Thu, 20 Jan 2022 12:20:49 +0000 (20:20 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 21 Jan 2022 05:52:57 +0000 (15:52 +1000)
commitf310df58bd2c570be8b802bffb37cb30da0c346e
tree13816edd3522a9ced3b1f4c41c69d55c2d5a93eftree | snapshot
parent5a2ae2350e78cfdc7ca9885b8c3d62137115a494commit | diff
target/riscv: Enable uxl field write

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220120122050.41546-23-zhiwei_liu@c-sky.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/cpu_bits.h diff | blob | history
target/riscv/csr.c diff | blob | history
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