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target-arm: Implement auxiliary fault status registers
authorPeter Maydell <peter.maydell@linaro.org>
Tue, 15 Apr 2014 18:18:47 +0000 (19:18 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Thu, 17 Apr 2014 20:34:05 +0000 (21:34 +0100)
commitf32cdad55de242a23aae9842cdb659e6de116352
treebc79b7f88127ad260932de5f3cda6da57fd2644dtree | snapshot
parent9449fdf61fc32e50e29d9bc5b531f1d238c13c97commit | diff
target-arm: Implement auxiliary fault status registers

Implement the auxiliary fault status registers AFSR0_EL1 and
AFSR1_EL1. These are present on v7 and later, and have IMPDEF
behaviour; we choose to RAZ/WI for all cores.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
target-arm/helper.c diff | blob | history
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