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MIPS: lantiq: enable pci clk conditional for xrx200 SoC
authorJohn Crispin <blogic@openwrt.org>
Thu, 16 Aug 2012 08:25:42 +0000 (08:25 +0000)
committerJohn Crispin <blogic@openwrt.org>
Wed, 22 Aug 2012 22:08:18 +0000 (00:08 +0200)
commitf40e1f9d856ec417468c090c4b56826171daa670
tree473073168643374dfec8caca3199286c85705793tree | snapshot
parent3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67acommit | diff
MIPS: lantiq: enable pci clk conditional for xrx200 SoC

The xrx200 SoC family has the same PCI clock register layout as the AR9.
Enable the same quirk as for AR9

Signed-off-by: John Crispin <blogic@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/4235/
arch/mips/lantiq/xway/sysctrl.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git