dt-bindings: riscv: correct e51 and u54-mc CPU bindings
authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Mon, 20 Sep 2021 13:25:59 +0000 (15:25 +0200)
committerRob Herring <robh@kernel.org>
Mon, 20 Sep 2021 22:00:32 +0000 (17:00 -0500)
commitf46428f066dda4792760d2843f6b3addd0054ab7
treee68a5529169254c7108198060fe9bb3af854a9e5
parent6f4276ecc0f7c9eb4a6fa24f8c7c92ce527d0724
dt-bindings: riscv: correct e51 and u54-mc CPU bindings

All existing boards with sifive,e51 and sifive,u54-mc use it on top of
sifive,rocket0 compatible:

  arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: cpu@0: compatible: 'oneOf' conditional failed, one must be fixed:
    ['sifive,e51', 'sifive,rocket0', 'riscv'] is too long
    Additional items are not allowed ('riscv' was unexpected)
    Additional items are not allowed ('sifive,rocket0', 'riscv' were unexpected)
    'riscv' was expected

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920132559.151678-1-krzysztof.kozlowski@canonical.com
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/riscv/cpus.yaml