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(parent: 79f5d67) | patch
hw/arm_gic: fix target CPUs affected by set enable/pending ops
authorDaniel Sangorrin <dsl@ertl.jp>
Tue, 11 Dec 2012 11:30:38 +0000 (11:30 +0000)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 11 Dec 2012 11:30:38 +0000 (11:30 +0000)
commitf47b48fb678581d6ee369cfe26b3513100b7d53e
treeef033c1a0378a9333b650020b622e6f4d18cc5b9tree | snapshot
parent79f5d67e9db35d53b478699393590392f7be03accommit | diff
hw/arm_gic: fix target CPUs affected by set enable/pending ops

Fix a bug on the ARM GIC model where interrupts are not
set pending on the correct target CPUs when they are
triggered by writes to the Interrupt Set Enable or
Set Pending registers.

Signed-off-by: Daniel Sangorrin <dsl@ertl.jp>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm_gic.c diff | blob | history
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