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(parent: 999ae6e) | patch
drm/msm/adreno: Read the speed bins for a5xx targets
authorJordan Crouse <jcrouse@codeaurora.org>
Tue, 21 Nov 2017 19:40:56 +0000 (12:40 -0700)
committerRob Clark <robdclark@gmail.com>
Wed, 10 Jan 2018 13:58:42 +0000 (08:58 -0500)
commitf56d9df656c41b141399c1edbcc9b0ed048120c2
tree50b17f3c9461c2d04e3627e74b60f77408f69f41tree | snapshot
parent999ae6edc1c19e316dd61f4b3e1a6984ea293280commit | diff
drm/msm/adreno: Read the speed bins for a5xx targets

Some 5xx based chipsets have different bins for GPU clock speeds.
Read the fuses (if applicable) and set the appropriate OPP table.
This will only work with OPP v2 tables - the bin will be ignored
for legacy pwrlevel tables.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
drivers/gpu/drm/msm/adreno/a5xx_gpu.c diff | blob | history
ep93xx device tree rework repo: git://git.maquefel.me/linux.git