RISC-V: KVM: Add support for SBI STA registers
authorAndrew Jones <ajones@ventanamicro.com>
Wed, 20 Dec 2023 16:00:21 +0000 (17:00 +0100)
committerAnup Patel <anup@brainfault.org>
Sat, 30 Dec 2023 05:56:35 +0000 (11:26 +0530)
commitf61ce890b1f0742f17b3a5d1f8c72574a33ffeb2
treef17c2b49c6e15c984ed6b50effbe5a943ec4f7b6
parent5b9e41321ba919dd051c68d2a1d2c753aa61634c
RISC-V: KVM: Add support for SBI STA registers

KVM userspace needs to be able to save and restore the steal-time
shared memory address. Provide the address through the get/set-one-reg
interface with two ulong-sized SBI STA extension registers (lo and hi).
64-bit KVM userspace must not set the hi register to anything other
than zero and is allowed to completely neglect saving/restoring it.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
arch/riscv/include/asm/kvm_vcpu_sbi.h
arch/riscv/include/uapi/asm/kvm.h
arch/riscv/kvm/vcpu_onereg.c
arch/riscv/kvm/vcpu_sbi.c
arch/riscv/kvm/vcpu_sbi_sta.c