target/arm: Implement new VFP fp16 insn VMOVX
authorPeter Maydell <peter.maydell@linaro.org>
Fri, 28 Aug 2020 18:33:29 +0000 (19:33 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 1 Sep 2020 10:19:32 +0000 (11:19 +0100)
commitf61e5c43b86907dea17f431b528d806659d62bcb
treec0a0f2e77f4b00d2c3f83647f1eaccac269ca32f
parente4875e3bcc3a9c54d7e074c8f51e04c2e6364e2e
target/arm: Implement new VFP fp16 insn VMOVX

The fp16 extension includes a new instruction VMOVX, which copies the
upper 16 bits of a 32-bit source VFP register into the lower 16
bits of the destination and zeroes the high half of the destination.
Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-21-peter.maydell@linaro.org
target/arm/translate-vfp.c.inc
target/arm/vfp-uncond.decode