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(parent: fb82fea) | patch
64bit MIPS FPUs have 32 registers.
authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 5 Apr 2007 23:14:23 +0000 (23:14 +0000)
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Thu, 5 Apr 2007 23:14:23 +0000 (23:14 +0000)
commitf7cfb2a176208d3b5139a2e792b40edf1adb43b4
treee8d411ece526a47140f58225bfc4b7b751230783tree | snapshot
parentfb82fea06403d7d7b064b9ef7acc9c62dcd52850commit | diff
64bit MIPS FPUs have 32 registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
target-mips/cpu.h diff | blob | history
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