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(parent: 91a51fe) | patch
target/ppc: 74xx: Set SRRs directly in exception code
authorFabiano Rosas <farosas@linux.ibm.com>
Fri, 28 Jan 2022 12:15:07 +0000 (13:15 +0100)
committerCédric Le Goater <clg@kaod.org>
Fri, 28 Jan 2022 12:15:07 +0000 (13:15 +0100)
commitf82db77761806613a62f622db9c1ca613ae1e6ed
tree218a079b24b1e6e6f19556470dcf1f83729f98edtree | snapshot
parent91a51fecef20ba4ee659a68a55b2b556f070908dcommit | diff
target/ppc: 74xx: Set SRRs directly in exception code

The 74xx does not have alternate/hypervisor Save and Restore
Registers, so we can set SRR0 and SRR1 directly.

Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com>
Message-Id: <20220127201116.1154733-9-farosas@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
target/ppc/excp_helper.c diff | blob | history
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