x86/perf/zhaoxin: Add stepping check for ZXC
authorsilviazhao <silviazhao-oc@zhaoxin.com>
Wed, 8 Feb 2023 08:27:22 +0000 (16:27 +0800)
committerPeter Zijlstra <peterz@infradead.org>
Sat, 11 Feb 2023 10:18:12 +0000 (11:18 +0100)
commitfd636b6a9bc6034f2e5bb869658898a2b472c037
treeea25b1fe7f1f912f0854adc246bc59b3d4414b45
parent89e97eb8cec0f1af5ebf2380308913256ca7915a
x86/perf/zhaoxin: Add stepping check for ZXC

Some of Nano series processors will lead GP when accessing
PMC fixed counter. Meanwhile, their hardware support for PMC
has not announced externally. So exclude Nano CPUs from ZXC
by checking stepping information. This is an unambiguous way
to differentiate between ZXC and Nano CPUs.

Following are Nano and ZXC FMS information:
Nano FMS: Family=6, Model=F, Stepping=[0-A][C-D]
ZXC FMS:  Family=6, Model=F, Stepping=E-F OR
          Family=6, Model=0x19, Stepping=0-3

Fixes: 3a4ac121c2ca ("x86/perf: Add hardware performance events support for Zhaoxin CPU.")
Reported-by: Arjan <8vvbbqzo567a@nospam.xutrox.com>
Reported-by: Kevin Brace <kevinbrace@gmx.com>
Signed-off-by: silviazhao <silviazhao-oc@zhaoxin.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=212389
arch/x86/events/zhaoxin/core.c