drm/i915/xehp: Check new fuse bits for SFC availability
authorMatt Roper <matthew.d.roper@intel.com>
Fri, 17 Sep 2021 16:12:02 +0000 (09:12 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 21 Sep 2021 04:42:09 +0000 (21:42 -0700)
commitff04f8beade56fead722d3f0ebcf63d4ab38e34d
tree62e62611f19b21de666ca31bae303d6f25694ed6
parent91160c8398243228dce619330fee600b4ad3a0f2
drm/i915/xehp: Check new fuse bits for SFC availability

Xe_HP adds some new bits to the FUSE1 register to let us know whether a
given SFC unit is present.  We should take this into account while
initializing SFC availability to our VCS and VECS engines.

While we're at it, update the FUSE1 register definition to use
REG_GENMASK / REG_FIELD_GET notation.

Note that, the bspec confusingly names the fuse bits "disable" despite
the register reflecting the *enable* status of the SFC units.  The
original architecture documents which the bspec is based on do properly
name this field "SFC_ENABLE."

Bspec: 52543
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210917161203.812251-2-matthew.d.roper@intel.com
drivers/gpu/drm/i915/gt/intel_engine_cs.c
drivers/gpu/drm/i915/gt/intel_gt_types.h
drivers/gpu/drm/i915/gt/intel_sseu.c
drivers/gpu/drm/i915/i915_reg.h