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target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns
authorSiarhei Volkau <lis8215@gmail.com>
Thu, 8 Jun 2023 10:41:56 +0000 (13:41 +0300)
committerPhilippe Mathieu-Daudé <philmd@linaro.org>
Mon, 10 Jul 2023 21:33:38 +0000 (23:33 +0200)
commitff7936f0093fab939bf4a8bff316b2cbd7f9f35f
tree2f6ebed0892a3fc6317bd098cdfac57520332613tree | snapshot
parentfc34c76f365a110977234ddcaaba4198dcd4c397commit | diff
target/mips/mxu: Add S32SLT D16SLT D16AVG[R] Q8AVG[R] insns

These instructions are part of pool1, see the grand tree above
in the file. Q8ADD is part of pool1 too but belong to another
category of instructions, thus will be made in later patches.

Signed-off-by: Siarhei Volkau <lis8215@gmail.com>
Message-Id: <20230608104222.1520143-8-lis8215@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
target/mips/tcg/mxu_translate.c diff | blob | history
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