projects / qemu.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: 7d04ac3) | patch
target/riscv: fix counter-enable checks in ctr()
authorXi Wang <xi.wang@gmail.com>
Sat, 26 Jan 2019 23:02:56 +0000 (15:02 -0800)
committerPalmer Dabbelt <palmer@sifive.com>
Mon, 11 Feb 2019 23:56:22 +0000 (15:56 -0800)
commitff9f31d9a0d45da83f34207b7ccace850cfc465b
treeb7534aab035d6dc28eac82d16325b8c6f484db19tree | snapshot
parent7d04ac38959f8115f2a029d81db1c8aac179aa95commit | diff
target/riscv: fix counter-enable checks in ctr()

Access to a counter in U-mode is permitted only if the corresponding
bit is set in both mcounteren and scounteren.  The current code
ignores mcounteren and checks scounteren only for U-mode access.

Signed-off-by: Xi Wang <xi.wang@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
target/riscv/csr.c diff | blob | history
Unnamed repository; edit this file 'description' to name the repository.