drm/amdgpu: open GFX clock gating for sienna_cichlid
authorLikun Gao <Likun.Gao@amd.com>
Thu, 23 Jan 2020 19:57:55 +0000 (03:57 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:10 +0000 (01:59 -0400)
Open GFX MGCG, CGCG and 3DCG for sienna_cichlid.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/nv.c

index 320d4db471cb15be020d8af9ae374c9acf16e97a..5d1c2eba34129986edb7cf6977436f09a9b7b910 100644 (file)
@@ -714,7 +714,10 @@ static int nv_common_early_init(void *handle)
                adev->external_rev_id = adev->rev_id + 0xa;
                break;
        case CHIP_SIENNA_CICHLID:
-               adev->cg_flags = AMD_CG_SUPPORT_VCN_MGCG |
+               adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
+                       AMD_CG_SUPPORT_GFX_CGCG |
+                       AMD_CG_SUPPORT_GFX_3D_CGCG |
+                       AMD_CG_SUPPORT_VCN_MGCG |
                        AMD_CG_SUPPORT_JPEG_MGCG;
                adev->pg_flags = AMD_PG_SUPPORT_VCN |
                        AMD_PG_SUPPORT_JPEG;