dmaengine: fsl-edma: support little endian for edma driver

Our platforms with below registers(CHCFG0 - CHCFG15) of eDMA
*-----------------------------------------------------------*
|     Offset   | Big endian Register| Little endian Register|
|--------------|--------------------|-----------------------|
|     0x0      |        CHCFG0      |           CHCFG3      |
|--------------|--------------------|-----------------------|
|     0x1      |        CHCFG1      |           CHCFG2      |
|--------------|--------------------|-----------------------|
|     0x2      |        CHCFG2      |           CHCFG1      |
|--------------|--------------------|-----------------------|
|     0x3      |        CHCFG3      |           CHCFG0      |
|--------------|--------------------|-----------------------|
|     ...      |        ......      |           ......      |
|--------------|--------------------|-----------------------|
|     0xC      |        CHCFG12     |           CHCFG15     |
|--------------|--------------------|-----------------------|
|     0xD      |        CHCFG13     |           CHCFG14     |
|--------------|--------------------|-----------------------|
|     0xE      |        CHCFG14     |           CHCFG13     |
|--------------|--------------------|-----------------------|
|     0xF      |        CHCFG15     |           CHCFG12     |
*-----------------------------------------------------------*

Current eDMA driver does not support Little endian, so this
patch is to improve edma driver to support little endian.

Signed-off-by: Peng Ma <peng.ma@nxp.com>
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c
index 680b2a00a953221547383a082af38f413d063502..6bf238e19d91da5ac09633c9cee87e8f6bc22f2f 100644 (file)
--- a/drivers/dma/fsl-edma-common.c
+++ b/drivers/dma/fsl-edma-common.c
@@ -83,9 +83,14 @@ void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
        u32 ch = fsl_chan->vchan.chan.chan_id;
        void __iomem *muxaddr;
        unsigned int chans_per_mux, ch_off;
+       int endian_diff[4] = {3, 1, -1, -3};
 
        chans_per_mux = fsl_chan->edma->n_chans / DMAMUX_NR;
        ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
+
+       if (!fsl_chan->edma->big_endian)
+               ch_off += endian_diff[ch_off % 4];
+
        muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
        slot = EDMAMUX_CHCFG_SOURCE(slot);