dt-bindings: clock: r9a07g043-cpg: Annotate RZ/G2UL-only core clocks

The M2 (CRU main clock), M3 (LCDC Video Clock), and AT (Cortex-A55 Debug
clock) core clocks are only present on RZ/G2UL, not on RZ/Five.

Annotate this in the comments, like is already done for module clocks
and resets.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/ffcdcd479c76b92f67481836a33ec86e97f85634.1708944903.git.geert+renesas@glider.be

diff --git a/include/dt-bindings/clock/r9a07g043-cpg.h b/include/dt-bindings/clock/r9a07g043-cpg.h
index 77cde8effdc73c6f68b3775b995034f8553fb106..a64139fec81520bf9efe2a145f52591acb01dcdd 100644 (file)
--- a/include/dt-bindings/clock/r9a07g043-cpg.h
+++ b/include/dt-bindings/clock/r9a07g043-cpg.h
@@ -16,15 +16,15 @@
 #define R9A07G043_CLK_SD0              5
 #define R9A07G043_CLK_SD1              6
 #define R9A07G043_CLK_M0               7
-#define R9A07G043_CLK_M2               8
-#define R9A07G043_CLK_M3               9
+#define R9A07G043_CLK_M2               8       /* RZ/G2UL Only */
+#define R9A07G043_CLK_M3               9       /* RZ/G2UL Only */
 #define R9A07G043_CLK_HP               10
 #define R9A07G043_CLK_TSU              11
 #define R9A07G043_CLK_ZT               12
 #define R9A07G043_CLK_P0               13
 #define R9A07G043_CLK_P1               14
 #define R9A07G043_CLK_P2               15
-#define R9A07G043_CLK_AT               16
+#define R9A07G043_CLK_AT               16      /* RZ/G2UL Only */
 #define R9A07G043_OSCCLK               17
 #define R9A07G043_CLK_P0_DIV2          18