drm/amd/display: Set FEC_READY always before link training

[why]
Right now we FEC_READY is set only before the final link training,
i.e. at mode set time. This means FEC_READY won't be set when doing
link training as a response to HPD. It also fails UCD400 FEC test in
DP compliance.

[how]
Move FEC_READY setup to link training.

Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Abdoulaye Berthe <Abdoulaye.Berthe@amd.com>
Acked-by: Leo Li <sunpeng.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link.c b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
index 0c9b6403177499a12f11bf9407d1454bf2ed7404..520d014a4ed866852938eaf071effe821fc18c28 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link.c
@@ -1523,15 +1523,6 @@ static enum dc_status enable_link_dp(
        if (link_settings.link_rate == LINK_RATE_LOW)
                        skip_video_pattern = false;
 
-#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
-       if (link->preferred_training_settings.fec_enable != NULL)
-               fec_enable = *link->preferred_training_settings.fec_enable;
-       else
-               fec_enable = true;
-
-       dp_set_fec_ready(link, fec_enable);
-#endif
-
        if (link->aux_access_disabled) {
                dc_link_dp_perform_link_training_skip_aux(link, &link_settings);
 
@@ -1549,6 +1540,11 @@ static enum dc_status enable_link_dp(
                status = DC_FAIL_DP_LINK_TRAINING;
 
 #ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+       if (link->preferred_training_settings.fec_enable != NULL)
+               fec_enable = *link->preferred_training_settings.fec_enable;
+       else
+               fec_enable = true;
+
        dp_set_fec_enable(link, fec_enable);
 #endif
        return status;

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 4442e7b1e5b5b6e2701e0781825b6c93ce2eb859..5c8e3318239cec3c3b250aa8dba7db285d85d129 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -1179,14 +1179,26 @@ enum link_training_result dc_link_dp_perform_link_training(
        bool skip_video_pattern)
 {
        enum link_training_result status = LINK_TRAINING_SUCCESS;
-
        struct link_training_settings lt_settings;
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+       bool fec_enable;
+#endif
 
        initialize_training_settings(link, link_setting, &lt_settings);
 
        /* 1. set link rate, lane count and spread. */
        dpcd_set_link_settings(link, &lt_settings);
 
+#ifdef CONFIG_DRM_AMD_DC_DSC_SUPPORT
+       if (link->preferred_training_settings.fec_enable != NULL)
+               fec_enable = *link->preferred_training_settings.fec_enable;
+       else
+               fec_enable = true;
+
+       dp_set_fec_ready(link, fec_enable);
+#endif
+
+
        /* 2. perform link training (set link training done
         *  to false is done as well)
         */
@@ -3153,7 +3165,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
 
        if (link_enc->funcs->fec_set_ready &&
                        link->dpcd_caps.fec_cap.bits.FEC_CAPABLE) {
-               if (link->fec_state == dc_link_fec_not_ready && ready) {
+               if (ready) {
                        fec_config = 1;
                        if (core_link_write_dpcd(link,
                                        DP_FEC_CONFIGURATION,
@@ -3164,7 +3176,7 @@ void dp_set_fec_ready(struct dc_link *link, bool ready)
                        } else {
                                dm_error("dpcd write failed to set fec_ready");
                        }
-               } else if (link->fec_state == dc_link_fec_ready && !ready) {
+               } else if (link->fec_state == dc_link_fec_ready) {
                        fec_config = 0;
                        core_link_write_dpcd(link,
                                        DP_FEC_CONFIGURATION,