hisi_acc_vfio_pci: Fix device data address combination problem
authorLongfang Liu <liulongfang@huawei.com>
Mon, 26 Sep 2022 09:33:29 +0000 (17:33 +0800)
committerAlex Williamson <alex.williamson@redhat.com>
Tue, 27 Sep 2022 15:30:31 +0000 (09:30 -0600)
The queue address of the accelerator device should be combined into
a dma address in a way of combining the low and high bits.
The previous combination is wrong and needs to be modified.

Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Signed-off-by: Longfang Liu <liulongfang@huawei.com>
Link: https://lore.kernel.org/r/20220926093332.28824-3-liulongfang@huawei.com
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
drivers/vfio/pci/hisilicon/hisi_acc_vfio_pci.c

index 4ef9761ef467525648acda5b028b45a6fa5e6938..fbe72ce173de0c089b269aae34fd42d4a904fe8b 100644 (file)
@@ -520,12 +520,12 @@ static int vf_qm_state_save(struct hisi_acc_vf_core_device *hisi_acc_vdev,
                return -EINVAL;
 
        /* Every reg is 32 bit, the dma address is 64 bit. */
-       vf_data->eqe_dma = vf_data->qm_eqc_dw[2];
+       vf_data->eqe_dma = vf_data->qm_eqc_dw[1];
        vf_data->eqe_dma <<= QM_XQC_ADDR_OFFSET;
-       vf_data->eqe_dma |= vf_data->qm_eqc_dw[1];
-       vf_data->aeqe_dma = vf_data->qm_aeqc_dw[2];
+       vf_data->eqe_dma |= vf_data->qm_eqc_dw[0];
+       vf_data->aeqe_dma = vf_data->qm_aeqc_dw[1];
        vf_data->aeqe_dma <<= QM_XQC_ADDR_OFFSET;
-       vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[1];
+       vf_data->aeqe_dma |= vf_data->qm_aeqc_dw[0];
 
        /* Through SQC_BT/CQC_BT to get sqc and cqc address */
        ret = qm_get_sqc(vf_qm, &vf_data->sqc_dma);