iio: dac: ad5504: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Fixes: 0dbe59c7a788 ("iio:ad5504: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-48-jic23@kernel.org

diff --git a/drivers/iio/dac/ad5504.c b/drivers/iio/dac/ad5504.c
index a0817e799cc075a9d745fe7b55d4b0153a3e65de..e6c5be728bb211032629ab7f1d8b288b050bb1a2 100644 (file)
--- a/drivers/iio/dac/ad5504.c
+++ b/drivers/iio/dac/ad5504.c
@@ -54,7 +54,7 @@ struct ad5504_state {
        unsigned                        pwr_down_mask;
        unsigned                        pwr_down_mode;
 
-       __be16                          data[2] ____cacheline_aligned;
+       __be16                          data[2] __aligned(IIO_DMA_MINALIGN);
 };
 
 /*