#include "dma_private.h"
#endif /* __INLINE_DMA__ */
-void dma_get_state(const dma_ID_t ID, dma_state_t *state)
-{
- int i;
- hrt_data tmp;
-
- assert(ID < N_DMA_ID);
- assert(state);
-
- tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX);
- //reg [3:0] : flags error [3], stall, run, idle [0]
- //reg [9:4] : command
- //reg[14:10] : channel
- //reg [23:15] : param
- state->fsm_command_idle = tmp & 0x1;
- state->fsm_command_run = tmp & 0x2;
- state->fsm_command_stalling = tmp & 0x4;
- state->fsm_command_error = tmp & 0x8;
- state->last_command_channel = (tmp >> 10 & 0x1F);
- state->last_command_param = (tmp >> 15 & 0x0F);
- tmp = (tmp >> 4) & 0x3F;
- /* state->last_command = (dma_commands_t)tmp; */
- /* if the enumerator is made non-linear */
- /* AM: the list below does not cover all the cases*/
- /* and these are not correct */
- /* therefore for just dumpinmg this command*/
- state->last_command = tmp;
-
- /*
- if (tmp == 0)
- state->last_command = DMA_COMMAND_READ;
- if (tmp == 1)
- state->last_command = DMA_COMMAND_WRITE;
- if (tmp == 2)
- state->last_command = DMA_COMMAND_SET_CHANNEL;
- if (tmp == 3)
- state->last_command = DMA_COMMAND_SET_PARAM;
- if (tmp == 4)
- state->last_command = DMA_COMMAND_READ_SPECIFIC;
- if (tmp == 5)
- state->last_command = DMA_COMMAND_WRITE_SPECIFIC;
- if (tmp == 8)
- state->last_command = DMA_COMMAND_INIT;
- if (tmp == 12)
- state->last_command = DMA_COMMAND_INIT_SPECIFIC;
- if (tmp == 15)
- state->last_command = DMA_COMMAND_RST;
- */
-
- /* No sub-fields, idx = 0 */
- state->current_command = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX));
- state->current_addr_a = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX));
- state->current_addr_b = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX));
-
- tmp = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_idle = tmp & 0x1;
- state->fsm_ctrl_run = tmp & 0x2;
- state->fsm_ctrl_stalling = tmp & 0x4;
- state->fsm_ctrl_error = tmp & 0x8;
- tmp = tmp >> 4;
- /* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */
- if (tmp == 0)
- state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE;
- if (tmp == 1)
- state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV;
- if (tmp == 2)
- state->fsm_ctrl_state = DMA_CTRL_STATE_RCV;
- if (tmp == 3)
- state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ;
- if (tmp == 4)
- state->fsm_ctrl_state = DMA_CTRL_STATE_INIT;
- state->fsm_ctrl_source_dev = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_source_addr = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_source_stride = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_source_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_source_height = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_source_dev = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_dest_addr = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_dest_stride = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_source_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_dest_height = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_dest_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_source_elems = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
- state->fsm_ctrl_pack_extension = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX,
- _DMA_FSM_GROUP_FSM_CTRL_IDX));
-
- tmp = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_PACK_STATE_IDX,
- _DMA_FSM_GROUP_FSM_PACK_IDX));
- state->pack_idle = tmp & 0x1;
- state->pack_run = tmp & 0x2;
- state->pack_stalling = tmp & 0x4;
- state->pack_error = tmp & 0x8;
- state->pack_cnt_height = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX,
- _DMA_FSM_GROUP_FSM_PACK_IDX));
- state->pack_src_cnt_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX,
- _DMA_FSM_GROUP_FSM_PACK_IDX));
- state->pack_dest_cnt_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX,
- _DMA_FSM_GROUP_FSM_PACK_IDX));
-
- tmp = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_REQ_STATE_IDX,
- _DMA_FSM_GROUP_FSM_REQ_IDX));
- /* state->read_state = (dma_rw_states_t)tmp; */
- if (tmp == 0)
- state->read_state = DMA_RW_STATE_IDLE;
- if (tmp == 1)
- state->read_state = DMA_RW_STATE_REQ;
- if (tmp == 2)
- state->read_state = DMA_RW_STATE_NEXT_LINE;
- if (tmp == 3)
- state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL;
- state->read_cnt_height = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX,
- _DMA_FSM_GROUP_FSM_REQ_IDX));
- state->read_cnt_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX,
- _DMA_FSM_GROUP_FSM_REQ_IDX));
-
- tmp = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_WR_STATE_IDX,
- _DMA_FSM_GROUP_FSM_WR_IDX));
- /* state->write_state = (dma_rw_states_t)tmp; */
- if (tmp == 0)
- state->write_state = DMA_RW_STATE_IDLE;
- if (tmp == 1)
- state->write_state = DMA_RW_STATE_REQ;
- if (tmp == 2)
- state->write_state = DMA_RW_STATE_NEXT_LINE;
- if (tmp == 3)
- state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL;
- state->write_height = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX,
- _DMA_FSM_GROUP_FSM_WR_IDX));
- state->write_width = dma_reg_load(ID,
- DMA_CG_INFO_REG_IDX(
- _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX,
- _DMA_FSM_GROUP_FSM_WR_IDX));
-
- for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
- dma_port_state_t *port = &state->port_states[i];
-
- tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i));
- port->req_cs = ((tmp & 0x1) != 0);
- port->req_we_n = ((tmp & 0x2) != 0);
- port->req_run = ((tmp & 0x4) != 0);
- port->req_ack = ((tmp & 0x8) != 0);
-
- tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i));
- port->send_cs = ((tmp & 0x1) != 0);
- port->send_we_n = ((tmp & 0x2) != 0);
- port->send_run = ((tmp & 0x4) != 0);
- port->send_ack = ((tmp & 0x8) != 0);
-
- tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i));
- if (tmp & 0x1)
- port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL;
- if (tmp & 0x2)
- port->fifo_state = DMA_FIFO_STATE_FULL;
- if (tmp & 0x4)
- port->fifo_state = DMA_FIFO_STATE_EMPTY;
- port->fifo_counter = tmp >> 3;
- }
-
- for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
- dma_channel_state_t *ch = &state->channel_states[i];
-
- ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_PACKING_SETUP_PARAM)));
- ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_PACKING_SETUP_PARAM)));
- ch->height = dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_HEIGHT_PARAM));
- ch->stride_a = dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_STRIDE_A_PARAM));
- ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_ELEM_CROPPING_A_PARAM)));
- ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_ELEM_CROPPING_A_PARAM)));
- ch->width_a = dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_WIDTH_A_PARAM));
- ch->stride_b = dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_STRIDE_B_PARAM));
- ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_ELEM_CROPPING_B_PARAM)));
- ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_ELEM_CROPPING_B_PARAM)));
- ch->width_b = dma_reg_load(ID,
- DMA_CHANNEL_PARAM_REG_IDX(i,
- _DMA_WIDTH_B_PARAM));
- }
-}
-
void
dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn,
uint32_t max_burst_size)
const input_system_multiplex_t rhs,
input_system_config_flags_t *const flags);
-static inline void capture_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- capture_unit_state_t *state);
-
-static inline void acquisition_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- acquisition_unit_state_t *state);
-
-static inline void ctrl_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- ctrl_unit_state_t *state);
-
-static inline void mipi_port_get_state(
- const rx_ID_t ID,
- const enum mipi_port_id port_ID,
- mipi_port_state_t *state);
-
-static inline void rx_channel_get_state(
- const rx_ID_t ID,
- const unsigned int ch_id,
- rx_channel_state_t *state);
-
static void gp_device_rst(const gp_device_ID_t ID);
static void input_selector_cfg_for_sensor(const gp_device_ID_t ID);
const input_switch_cfg_t *const cfg
);
-void receiver_get_state(
- const rx_ID_t ID,
- receiver_state_t *state)
-{
- enum mipi_port_id port_id;
- unsigned int ch_id;
-
- assert(ID < N_RX_ID);
- assert(state);
-
- state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX);
- state->ls_to_data_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX);
- state->data_to_le_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX);
- state->le_to_fe_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX);
- state->fe_to_fs_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX);
- state->le_to_fs_delay = (uint8_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX);
- state->is_two_ppc = (bool)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX);
- state->backend_rst = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX);
- state->raw18 = (uint16_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_RAW18_REG_IDX);
- state->force_raw8 = (bool)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX);
- state->raw16 = (uint16_t)receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_RAW16_REG_IDX);
-
- for (port_id = (enum mipi_port_id)0; port_id < N_MIPI_PORT_ID; port_id++) {
- mipi_port_get_state(ID, port_id,
- &state->mipi_port_state[port_id]);
- }
- for (ch_id = 0U; ch_id < N_RX_CHANNEL_ID; ch_id++) {
- rx_channel_get_state(ID, ch_id,
- &state->rx_channel_state[ch_id]);
- }
-
- state->be_gsp_acc_ovl = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX);
- state->be_srst = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_SRST_REG_IDX);
- state->be_is_two_ppc = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX);
- state->be_comp_format0 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX);
- state->be_comp_format1 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX);
- state->be_comp_format2 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX);
- state->be_comp_format3 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX);
- state->be_sel = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_SEL_REG_IDX);
- state->be_raw16_config = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX);
- state->be_raw18_config = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX);
- state->be_force_raw8 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX);
- state->be_irq_status = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX);
- state->be_irq_clear = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX);
-}
-
void receiver_set_compression(
const rx_ID_t ID,
const unsigned int cfg_ID,
port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info);
}
-static inline void capture_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- capture_unit_state_t *state)
-{
- assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID));
- assert(state);
-
- state->StartMode = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_START_MODE_REG_ID);
- state->Start_Addr = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_START_ADDR_REG_ID);
- state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_MEM_REGION_SIZE_REG_ID);
- state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_NUM_MEM_REGIONS_REG_ID);
-// AM: Illegal read from following registers.
- /* state->Init = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_INIT_REG_ID);
- state->Start = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_START_REG_ID);
- state->Stop = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_STOP_REG_ID);
- */
- state->Packet_Length = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_PACKET_LENGTH_REG_ID);
- state->Received_Length = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_RECEIVED_LENGTH_REG_ID);
- state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_RECEIVED_SHORT_PACKETS_REG_ID);
- state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_RECEIVED_LONG_PACKETS_REG_ID);
- state->Last_Command = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_LAST_COMMAND_REG_ID);
- state->Next_Command = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_NEXT_COMMAND_REG_ID);
- state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_LAST_ACKNOWLEDGE_REG_ID);
- state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_NEXT_ACKNOWLEDGE_REG_ID);
- state->FSM_State_Info = input_system_sub_system_reg_load(ID,
- sub_id,
- CAPT_FSM_STATE_INFO_REG_ID);
-}
-
-static inline void acquisition_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- acquisition_unit_state_t *state)
-{
- assert(sub_id == ACQUISITION_UNIT0_ID);
- assert(state);
-
- state->Start_Addr = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_START_ADDR_REG_ID);
- state->Mem_Region_Size = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_MEM_REGION_SIZE_REG_ID);
- state->Num_Mem_Regions = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_NUM_MEM_REGIONS_REG_ID);
-// AM: Illegal read from following registers.
- /* state->Init = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_INIT_REG_ID);
- */
- state->Received_Short_Packets = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_RECEIVED_SHORT_PACKETS_REG_ID);
- state->Received_Long_Packets = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_RECEIVED_LONG_PACKETS_REG_ID);
- state->Last_Command = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_LAST_COMMAND_REG_ID);
- state->Next_Command = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_NEXT_COMMAND_REG_ID);
- state->Last_Acknowledge = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_LAST_ACKNOWLEDGE_REG_ID);
- state->Next_Acknowledge = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_NEXT_ACKNOWLEDGE_REG_ID);
- state->FSM_State_Info = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_FSM_STATE_INFO_REG_ID);
- state->Int_Cntr_Info = input_system_sub_system_reg_load(ID,
- sub_id,
- ACQ_INT_CNTR_INFO_REG_ID);
-}
-
-static inline void ctrl_unit_get_state(
- const input_system_ID_t ID,
- const sub_system_ID_t sub_id,
- ctrl_unit_state_t *state)
-{
- assert(sub_id == CTRL_UNIT0_ID);
- assert(state);
-
- state->captA_start_addr = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_START_ADDR_A_REG_ID);
- state->captB_start_addr = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_START_ADDR_B_REG_ID);
- state->captC_start_addr = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_START_ADDR_C_REG_ID);
- state->captA_mem_region_size = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID);
- state->captB_mem_region_size = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID);
- state->captC_mem_region_size = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID);
- state->captA_num_mem_regions = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID);
- state->captB_num_mem_regions = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID);
- state->captC_num_mem_regions = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID);
- state->acq_start_addr = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_ACQ_START_ADDR_REG_ID);
- state->acq_mem_region_size = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID);
- state->acq_num_mem_regions = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID);
-// AM: Illegal read from following registers.
- /* state->ctrl_init = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_INIT_REG_ID);
- */
- state->last_cmd = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_LAST_COMMAND_REG_ID);
- state->next_cmd = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_NEXT_COMMAND_REG_ID);
- state->last_ack = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID);
- state->next_ack = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID);
- state->top_fsm_state = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_FSM_STATE_INFO_REG_ID);
- state->captA_fsm_state = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID);
- state->captB_fsm_state = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID);
- state->captC_fsm_state = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID);
- state->acq_fsm_state = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID);
- state->capt_reserve_one_mem_region = input_system_sub_system_reg_load(ID,
- sub_id,
- ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID);
-}
-
-static inline void mipi_port_get_state(
- const rx_ID_t ID,
- const enum mipi_port_id port_ID,
- mipi_port_state_t *state)
-{
- int i;
-
- assert(ID < N_RX_ID);
- assert(port_ID < N_MIPI_PORT_ID);
- assert(state);
-
- state->device_ready = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX);
- state->irq_status = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX);
- state->irq_enable = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX);
- state->timeout_count = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX);
- state->init_count = (uint16_t)receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX);
- state->raw16_18 = (uint16_t)receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX);
- state->sync_count = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX);
- state->rx_count = receiver_port_reg_load(ID,
- port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX);
-
- for (i = 0; i < MIPI_4LANE_CFG ; i++) {
- state->lane_sync_count[i] = (uint8_t)((state->sync_count) >> (i * 8));
- state->lane_rx_count[i] = (uint8_t)((state->rx_count) >> (i * 8));
- }
-}
-
-static inline void rx_channel_get_state(
- const rx_ID_t ID,
- const unsigned int ch_id,
- rx_channel_state_t *state)
-{
- int i;
-
- assert(ID < N_RX_ID);
- assert(ch_id < N_RX_CHANNEL_ID);
- assert(state);
-
- switch (ch_id) {
- case 0:
- state->comp_scheme0 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX);
- state->comp_scheme1 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX);
- break;
- case 1:
- state->comp_scheme0 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX);
- state->comp_scheme1 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX);
- break;
- case 2:
- state->comp_scheme0 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX);
- state->comp_scheme1 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX);
- break;
- case 3:
- state->comp_scheme0 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX);
- state->comp_scheme1 = receiver_reg_load(ID,
- _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX);
- break;
- }
-
- /* See Table 7.1.17,..., 7.1.24 */
- for (i = 0; i < 6; i++) {
- u8 val = (uint8_t)((state->comp_scheme0) >> (i * 5)) & 0x1f;
-
- state->comp[i] = (mipi_compressor_t)(val & 0x07);
- state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
- }
- for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) {
- u8 val = (uint8_t)((state->comp_scheme0) >> ((i - 6) * 5)) & 0x1f;
-
- state->comp[i] = (mipi_compressor_t)(val & 0x07);
- state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3);
- }
-}
-
// MW: "2400" in the name is not good, but this is to avoid a naming conflict
static input_system_cfg2400_t config;
}
}
-static void debug_print_sp_state(const sp_state_t *state, const char *cell)
-{
- assert(cell);
- assert(state);
-
- ia_css_debug_dtrace(2, "%s state:\n", cell);
- ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
- ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
- state->status_register);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
- state->is_sleeping);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
- state->is_stalling);
- return;
-}
-
-static void debug_print_isp_state(const isp_state_t *state, const char *cell)
-{
- assert(state);
- assert(cell);
-
- ia_css_debug_dtrace(2, "%s state:\n", cell);
- ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc);
- ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register",
- state->status_register);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping",
- state->is_sleeping);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling",
- state->is_stalling);
- return;
-}
-
-void ia_css_debug_dump_isp_state(void)
-{
- isp_state_t state;
- isp_stall_t stall;
-
- isp_get_state(ISP0_ID, &state, &stall);
-
- debug_print_isp_state(&state, "ISP");
-
- if (state.is_stalling) {
- if (!IS_ISP2401) {
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "[0] if_prim_a_FIFO stalled", stall.fifo0);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "[1] if_prim_b_FIFO stalled", stall.fifo1);
- }
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled",
- stall.fifo2);
-
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled",
- stall.fifo3);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled",
- stall.fifo4);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled",
- stall.fifo5);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled",
- stall.fifo6);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "status & control stalled",
- stall.stat_ctrl);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
- stall.dmem);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled",
- stall.vmem);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled",
- stall.vamem1);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled",
- stall.vamem2);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled",
- stall.vamem3);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled",
- stall.hmem);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled",
- stall.pmem);
- }
- return;
-}
-
-void ia_css_debug_dump_sp_state(void)
-{
- sp_state_t state;
- sp_stall_t stall;
-
- sp_get_state(SP0_ID, &state, &stall);
- debug_print_sp_state(&state, "SP");
- if (state.is_stalling) {
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled",
- stall.fifo0);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled",
- stall.fifo1);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "str_to_mem_FIFO stalled", stall.fifo2);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled",
- stall.fifo3);
- if (!IS_ISP2401)
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "if_prim_a_FIFO stalled", stall.fifo4);
-
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled",
- stall.fifo5);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled",
- stall.fifo6);
- if (!IS_ISP2401)
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "if_prim_b_FIFO stalled", stall.fifo7);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled",
- stall.fifo8);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled",
- stall.fifo9);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled",
- stall.fifoa);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled",
- stall.dmem);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "control master stalled",
- stall.control_master);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n",
- "i-cache master stalled",
- stall.icache_master);
- }
- ia_css_debug_dump_trace();
- return;
-}
-
static void debug_print_fifo_channel_state(const fifo_channel_state_t *state,
const char *descr)
{
debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory");
}
-#ifndef ISP2401
-static void debug_print_if_state(input_formatter_state_t *state, const char *id)
-{
- unsigned int val;
-
- const char *st_vsync_active_low =
- (state->vsync_active_low ? "low" : "high");
- const char *st_hsync_active_low =
- (state->hsync_active_low ? "low" : "high");
-
- const char *fsm_sync_status_str = "unknown";
- const char *fsm_crop_status_str = "unknown";
- const char *fsm_padding_status_str = "unknown";
-
- int st_stline = state->start_line;
- int st_stcol = state->start_column;
- int st_crpht = state->cropped_height;
- int st_crpwd = state->cropped_width;
- int st_verdcm = state->ver_decimation;
- int st_hordcm = state->hor_decimation;
- int st_ver_deinterleaving = state->ver_deinterleaving;
- int st_hor_deinterleaving = state->hor_deinterleaving;
- int st_leftpd = state->left_padding;
- int st_eoloff = state->eol_offset;
- int st_vmstartaddr = state->vmem_start_address;
- int st_vmendaddr = state->vmem_end_address;
- int st_vmincr = state->vmem_increment;
- int st_yuv420 = state->is_yuv420;
- int st_allow_fifo_overflow = state->allow_fifo_overflow;
- int st_block_fifo_when_no_req = state->block_fifo_when_no_req;
-
- assert(state);
- ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id);
-
- ia_css_debug_dtrace(2, "\tConfiguration:\n");
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "Ver deinterleaving", st_ver_deinterleaving);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "Hor deinterleaving", st_hor_deinterleaving);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "EOL offset (bytes)", st_eoloff);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
- "VMEM start address", st_vmstartaddr);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
- "VMEM end address", st_vmendaddr);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n",
- "VMEM increment", st_vmincr);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420);
- ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
- "Vsync", st_vsync_active_low);
- ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n",
- "Hsync", st_hsync_active_low);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "Allow FIFO overflow", st_allow_fifo_overflow);
- /* Flag that tells whether the IF gives backpressure on frames */
- /*
- * FYI, this is only on the frame request (indicate), when the IF has
- * synch'd on a frame it will always give back pressure
- */
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "Block when no request", st_block_fifo_when_no_req);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "IF_BLOCKED_FIFO_NO_REQ_ADDRESS",
- input_formatter_reg_load(INPUT_FORMATTER0_ID,
- HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS)
- );
-
- ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State");
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg0",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg0));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg1",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg1));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg2",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg2));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg3",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg3));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg4",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg4));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg5",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg5));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg6",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg6));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_lut_reg7",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_lut_reg7));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_input_switch_fsync_lut",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_input_switch_fsync_lut));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_srst",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_srst));
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "_REG_GP_IFMT_slv_reg_srst",
- gp_device_reg_load(GP_DEVICE0_ID,
- _REG_GP_IFMT_slv_reg_srst));
-
- ia_css_debug_dtrace(2, "\tFSM Status:\n");
-
- val = state->fsm_sync_status;
-
- if (val > 7)
- fsm_sync_status_str = "ERROR";
-
- switch (val & 0x7) {
- case 0:
- fsm_sync_status_str = "idle";
- break;
- case 1:
- fsm_sync_status_str = "request frame";
- break;
- case 2:
- fsm_sync_status_str = "request lines";
- break;
- case 3:
- fsm_sync_status_str = "request vectors";
- break;
- case 4:
- fsm_sync_status_str = "send acknowledge";
- break;
- default:
- fsm_sync_status_str = "unknown";
- break;
- }
-
- ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
- "FSM Synchronization Status", val,
- fsm_sync_status_str);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM Synchronization Counter",
- state->fsm_sync_counter);
-
- val = state->fsm_crop_status;
-
- if (val > 7)
- fsm_crop_status_str = "ERROR";
-
- switch (val & 0x7) {
- case 0:
- fsm_crop_status_str = "idle";
- break;
- case 1:
- fsm_crop_status_str = "wait line";
- break;
- case 2:
- fsm_crop_status_str = "crop line";
- break;
- case 3:
- fsm_crop_status_str = "crop pixel";
- break;
- case 4:
- fsm_crop_status_str = "pass pixel";
- break;
- case 5:
- fsm_crop_status_str = "pass line";
- break;
- case 6:
- fsm_crop_status_str = "lost line";
- break;
- default:
- fsm_crop_status_str = "unknown";
- break;
- }
- ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n",
- "FSM Crop Status", val, fsm_crop_status_str);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM Crop Line Counter",
- state->fsm_crop_line_counter);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM Crop Pixel Counter",
- state->fsm_crop_pixel_counter);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM Deinterleaving idx buffer",
- state->fsm_deinterleaving_index);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM H decimation counter",
- state->fsm_dec_h_counter);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM V decimation counter",
- state->fsm_dec_v_counter);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM block V decimation counter",
- state->fsm_dec_block_v_counter);
-
- val = state->fsm_padding_status;
-
- if (val > 7)
- fsm_padding_status_str = "ERROR";
-
- switch (val & 0x7) {
- case 0:
- fsm_padding_status_str = "idle";
- break;
- case 1:
- fsm_padding_status_str = "left pad";
- break;
- case 2:
- fsm_padding_status_str = "write";
- break;
- case 3:
- fsm_padding_status_str = "right pad";
- break;
- case 4:
- fsm_padding_status_str = "send end of line";
- break;
- default:
- fsm_padding_status_str = "unknown";
- break;
- }
-
- ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status",
- val, fsm_padding_status_str);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "FSM Padding element idx counter",
- state->fsm_padding_elem_counter);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error",
- state->fsm_vector_support_error);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full",
- state->fsm_vector_buffer_full);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support",
- state->vector_support);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost",
- state->sensor_data_lost);
-}
-
-static void debug_print_if_bin_state(input_formatter_bin_state_t *state)
-{
- ia_css_debug_dtrace(2, "Stream-to-memory state:\n");
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness",
- state->input_endianness);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness",
- state->output_endianness);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch",
- state->block_synch);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch",
- state->packet_synch);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync",
- state->readpostwrite_synch);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc);
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update",
- state->en_status_update);
-}
-
-static void ia_css_debug_dump_if_state(void)
-{
- input_formatter_state_t if_state;
- input_formatter_bin_state_t if_bin_state;
-
- input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state);
- debug_print_if_state(&if_state, "Primary IF A");
- ia_css_debug_dump_pif_a_isp_fifo_state();
-
- input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state);
- debug_print_if_state(&if_state, "Primary IF B");
- ia_css_debug_dump_pif_b_isp_fifo_state();
-
- input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state);
- debug_print_if_bin_state(&if_bin_state);
- ia_css_debug_dump_str2mem_sp_fifo_state();
-}
-#endif
-
-void ia_css_debug_dump_dma_state(void)
-{
- /* note: the var below is made static as it is quite large;
- if it is not static it ends up on the stack which could
- cause issues for drivers
- */
- static dma_state_t state;
- int i, ch_id;
-
- const char *fsm_cmd_st_lbl = "FSM Command flag state";
- const char *fsm_ctl_st_lbl = "FSM Control flag state";
- const char *fsm_ctl_state = NULL;
- const char *fsm_ctl_flag = NULL;
- const char *fsm_pack_st = NULL;
- const char *fsm_read_st = NULL;
- const char *fsm_write_st = NULL;
- char last_cmd_str[64];
-
- dma_get_state(DMA0_ID, &state);
- /* Print header for DMA dump status */
- ia_css_debug_dtrace(2, "DMA dump status:\n");
-
- /* Print FSM command flag state */
- if (state.fsm_command_idle)
- ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE");
- if (state.fsm_command_run)
- ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN");
- if (state.fsm_command_stalling)
- ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
- "STALL");
- if (state.fsm_command_error)
- ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl,
- "ERROR");
-
- /* Print last command along with the channel */
- ch_id = state.last_command_channel;
-
- switch (state.last_command) {
- case DMA_COMMAND_READ:
- snprintf(last_cmd_str, 64,
- "Read 2D Block [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_WRITE:
- snprintf(last_cmd_str, 64,
- "Write 2D Block [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_SET_CHANNEL:
- snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_SET_PARAM:
- snprintf(last_cmd_str, 64,
- "Set Param: %d [Channel: %d]",
- state.last_command_param, ch_id);
- break;
- case DMA_COMMAND_READ_SPECIFIC:
- snprintf(last_cmd_str, 64,
- "Read Specific 2D Block [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_WRITE_SPECIFIC:
- snprintf(last_cmd_str, 64,
- "Write Specific 2D Block [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_INIT:
- snprintf(last_cmd_str, 64,
- "Init 2D Block on Device A [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_INIT_SPECIFIC:
- snprintf(last_cmd_str, 64,
- "Init Specific 2D Block [Channel: %d]", ch_id);
- break;
- case DMA_COMMAND_RST:
- snprintf(last_cmd_str, 64, "DMA SW Reset");
- break;
- case N_DMA_COMMANDS:
- snprintf(last_cmd_str, 64, "UNKNOWN");
- break;
- default:
- snprintf(last_cmd_str, 64,
- "unknown [Channel: %d]", ch_id);
- break;
- }
- ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n",
- "last command received", state.last_command,
- last_cmd_str);
-
- /* Print DMA registers */
- ia_css_debug_dtrace(2, "\t%-32s\n",
- "DMA registers, connection group 0");
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command",
- state.current_command);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A",
- state.current_addr_a);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B",
- state.current_addr_b);
-
- if (state.fsm_ctrl_idle)
- fsm_ctl_flag = "IDLE";
- else if (state.fsm_ctrl_run)
- fsm_ctl_flag = "RUN";
- else if (state.fsm_ctrl_stalling)
- fsm_ctl_flag = "STAL";
- else if (state.fsm_ctrl_error)
- fsm_ctl_flag = "ERROR";
- else
- fsm_ctl_flag = "UNKNOWN";
-
- switch (state.fsm_ctrl_state) {
- case DMA_CTRL_STATE_IDLE:
- fsm_ctl_state = "Idle state";
- break;
- case DMA_CTRL_STATE_REQ_RCV:
- fsm_ctl_state = "Req Rcv state";
- break;
- case DMA_CTRL_STATE_RCV:
- fsm_ctl_state = "Rcv state";
- break;
- case DMA_CTRL_STATE_RCV_REQ:
- fsm_ctl_state = "Rcv Req state";
- break;
- case DMA_CTRL_STATE_INIT:
- fsm_ctl_state = "Init state";
- break;
- case N_DMA_CTRL_STATES:
- fsm_ctl_state = "Unknown";
- break;
- }
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl,
- fsm_ctl_flag, fsm_ctl_state);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev",
- state.fsm_ctrl_source_dev);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr",
- state.fsm_ctrl_source_addr);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride",
- state.fsm_ctrl_source_stride);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width",
- state.fsm_ctrl_source_width);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height",
- state.fsm_ctrl_source_height);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev",
- state.fsm_ctrl_pack_source_dev);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev",
- state.fsm_ctrl_pack_dest_dev);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr",
- state.fsm_ctrl_dest_addr);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride",
- state.fsm_ctrl_dest_stride);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width",
- state.fsm_ctrl_pack_source_width);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height",
- state.fsm_ctrl_pack_dest_height);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width",
- state.fsm_ctrl_pack_dest_width);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems",
- state.fsm_ctrl_pack_source_elems);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems",
- state.fsm_ctrl_pack_dest_elems);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension",
- state.fsm_ctrl_pack_extension);
-
- if (state.pack_idle)
- fsm_pack_st = "IDLE";
- if (state.pack_run)
- fsm_pack_st = "RUN";
- if (state.pack_stalling)
- fsm_pack_st = "STALL";
- if (state.pack_error)
- fsm_pack_st = "ERROR";
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state",
- fsm_pack_st);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height",
- state.pack_cnt_height);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width",
- state.pack_src_cnt_width);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width",
- state.pack_dest_cnt_width);
-
- if (state.read_state == DMA_RW_STATE_IDLE)
- fsm_read_st = "Idle state";
- if (state.read_state == DMA_RW_STATE_REQ)
- fsm_read_st = "Req state";
- if (state.read_state == DMA_RW_STATE_NEXT_LINE)
- fsm_read_st = "Next line";
- if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL)
- fsm_read_st = "Unlock channel";
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state",
- fsm_read_st);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height",
- state.read_cnt_height);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width",
- state.read_cnt_width);
-
- if (state.write_state == DMA_RW_STATE_IDLE)
- fsm_write_st = "Idle state";
- if (state.write_state == DMA_RW_STATE_REQ)
- fsm_write_st = "Req state";
- if (state.write_state == DMA_RW_STATE_NEXT_LINE)
- fsm_write_st = "Next line";
- if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL)
- fsm_write_st = "Unlock channel";
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state",
- fsm_write_st);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height",
- state.write_height);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width",
- state.write_width);
-
- for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) {
- dma_port_state_t *port = &state.port_states[i];
-
- ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i);
- ia_css_debug_dtrace(2, "\t\tDMA internal side state\n");
- ia_css_debug_dtrace(2,
- "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
- port->req_cs, port->req_we_n, port->req_run,
- port->req_ack);
- ia_css_debug_dtrace(2, "\t\tMaster Output side state\n");
- ia_css_debug_dtrace(2,
- "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n",
- port->send_cs, port->send_we_n,
- port->send_run, port->send_ack);
- ia_css_debug_dtrace(2, "\t\tFifo state\n");
- if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL)
- ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n");
- else if (port->fifo_state == DMA_FIFO_STATE_FULL)
- ia_css_debug_dtrace(2, "\t\t\tFifo Full\n");
- else if (port->fifo_state == DMA_FIFO_STATE_EMPTY)
- ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n");
- else
- ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n");
-
- ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n",
- port->fifo_counter);
- }
-
- for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) {
- dma_channel_state_t *ch = &state.channel_states[i];
-
- ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register",
- i);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection",
- ch->connection);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend",
- ch->sign_extend);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A",
- ch->stride_a);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A",
- ch->elems_a);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A",
- ch->cropping_a);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A",
- ch->width_a);
- ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B",
- ch->stride_b);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B",
- ch->elems_b);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B",
- ch->cropping_b);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B",
- ch->width_b);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height);
- }
- ia_css_debug_dtrace(2, "\n");
- return;
-}
-
-void ia_css_debug_dump_dma_sp_fifo_state(void)
-{
- fifo_channel_state_t dma_to_sp, sp_to_dma;
-
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp);
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma);
- debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP");
- debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA");
- return;
-}
-
-void ia_css_debug_dump_dma_isp_fifo_state(void)
-{
- fifo_channel_state_t dma_to_isp, isp_to_dma;
-
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp);
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma);
- debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP");
- debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA");
- return;
-}
-
-void ia_css_debug_dump_isp_sp_fifo_state(void)
-{
- fifo_channel_state_t sp_to_isp, isp_to_sp;
-
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp);
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp);
- debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP");
- debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP");
- return;
-}
-
-void ia_css_debug_dump_isp_gdc_fifo_state(void)
-{
- fifo_channel_state_t gdc_to_isp, isp_to_gdc;
-
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp);
- fifo_channel_get_state(FIFO_MONITOR0_ID,
- FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc);
- debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP");
- debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC");
- return;
-}
-
void ia_css_debug_dump_all_fifo_state(void)
{
int i;
}
#endif
-#if !defined(ISP2401)
-static void debug_print_rx_mipi_port_state(mipi_port_state_t *state)
-{
- int i;
- unsigned int bits, infos;
-
- assert(state);
-
- bits = state->irq_status;
- infos = ia_css_isys_rx_translate_irq_infos(bits);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n",
- "receiver errors", bits);
-
- if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN)
- ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT)
- ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC)
- ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL)
- ia_css_debug_dtrace(2, "\t\t\tcontrol error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE)
- ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC)
- ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID)
- ia_css_debug_dtrace(2, "\t\t\tunknown error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC)
- ia_css_debug_dtrace(2, "\t\t\tframe sync error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA)
- ia_css_debug_dtrace(2, "\t\t\tframe data error\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT)
- ia_css_debug_dtrace(2, "\t\t\tdata timeout\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC)
- ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n");
- if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC)
- ia_css_debug_dtrace(2, "\t\t\tline sync error\n");
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "device_ready", state->device_ready);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_status", state->irq_status);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_enable", state->irq_enable);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "timeout_count", state->timeout_count);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "init_count", state->init_count);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "sync_count", state->sync_count);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count);
-
- for (i = 0; i < MIPI_4LANE_CFG; i++) {
- ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
- "lane_sync_count[", i, "]",
- state->lane_sync_count[i]);
- }
-
- for (i = 0; i < MIPI_4LANE_CFG; i++) {
- ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n",
- "lane_rx_count[", i, "]",
- state->lane_rx_count[i]);
- }
-
- return;
-}
-
-static void debug_print_rx_channel_state(rx_channel_state_t *state)
-{
- int i;
-
- assert(state);
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "compression_scheme0", state->comp_scheme0);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "compression_scheme1", state->comp_scheme1);
-
- for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
- ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
- "MIPI Predictor ", i, state->pred[i]);
- }
-
- for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) {
- ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n",
- "MIPI Compressor ", i, state->comp[i]);
- }
-
- return;
-}
-
-static void debug_print_rx_state(receiver_state_t *state)
-{
- int i;
-
- assert(state);
- ia_css_debug_dtrace(2, "CSI Receiver State:\n");
-
- ia_css_debug_dtrace(2, "\tConfiguration:\n");
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "fs_to_ls_delay", state->fs_to_ls_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "ls_to_data_delay", state->ls_to_data_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "data_to_le_delay", state->data_to_le_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "le_to_fe_delay", state->le_to_fe_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "fe_to_fs_delay", state->fe_to_fs_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "le_to_fs_delay", state->le_to_fs_delay);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "is_two_ppc", state->is_two_ppc);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "backend_rst", state->backend_rst);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "force_raw8", state->force_raw8);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_gsp_acc_ovl", state->be_gsp_acc_ovl);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_is_two_ppc", state->be_is_two_ppc);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_comp_format0", state->be_comp_format0);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_comp_format1", state->be_comp_format1);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_comp_format2", state->be_comp_format2);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_comp_format3", state->be_comp_format3);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_raw16_config", state->be_raw16_config);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_raw18_config", state->be_raw18_config);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_force_raw8", state->be_force_raw8);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_irq_status", state->be_irq_status);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "be_irq_clear", state->be_irq_clear);
-
- /* mipi port state */
- for (i = 0; i < N_MIPI_PORT_ID; i++) {
- ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i);
-
- debug_print_rx_mipi_port_state(&state->mipi_port_state[i]);
- }
- /* end of mipi port state */
-
- /* rx channel state */
- for (i = 0; i < N_RX_CHANNEL_ID; i++) {
- ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i);
-
- debug_print_rx_channel_state(&state->rx_channel_state[i]);
- }
- /* end of rx channel state */
-
- return;
-}
-#endif
-
-void ia_css_debug_dump_rx_state(void)
-{
-#if !defined(ISP2401)
- receiver_state_t state;
-
- receiver_get_state(RX0_ID, &state);
- debug_print_rx_state(&state);
-#endif
-}
-
void ia_css_debug_dump_sp_sw_debug_info(void)
{
#if SP_DEBUG != SP_DEBUG_NONE
return;
}
-void ia_css_debug_dump_debug_info(const char *context)
-{
- if (!context)
- context = "No Context provided";
-
- ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context);
- if (!IS_ISP2401)
- ia_css_debug_dump_rx_state();
-
-#ifndef ISP2401
- ia_css_debug_dump_if_state();
-#endif
- ia_css_debug_dump_isp_state();
- ia_css_debug_dump_isp_sp_fifo_state();
- ia_css_debug_dump_isp_gdc_fifo_state();
- ia_css_debug_dump_sp_state();
- ia_css_debug_dump_perf_counters();
- ia_css_debug_dump_dma_isp_fifo_state();
- ia_css_debug_dump_dma_sp_fifo_state();
- ia_css_debug_dump_dma_state();
-
- if (!IS_ISP2401) {
- struct irq_controller_state state;
-
- irq_controller_get_state(IRQ2_ID, &state);
-
- ia_css_debug_dtrace(2, "\t%-32s:\n",
- "Input System IRQ Controller State");
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_edge", state.irq_edge);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_mask", state.irq_mask);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_status", state.irq_status);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_enable", state.irq_enable);
-
- ia_css_debug_dtrace(2, "\t\t%-32s: %d\n",
- "irq_level_not_pulse",
- state.irq_level_not_pulse);
- }
-
- ia_css_debug_tagger_state();
-
- return;
-}
-
/* this function is for debug use, it can make SP go to sleep
state after each frame, then user can dump the stable SP dmem.
this function can be called after ia_css_start_sp()
}
}
-void ia_css_debug_dump_perf_counters(void)
-{
- const struct ia_css_fw_info *fw;
- int i;
- unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt;
- /* N_MIPI_PORT_ID + 1: 3 Capture Units and 1 Acquire Unit. */
- s32 ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1];
-
- if (IS_ISP2401)
- return;
-
- ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n");
-
- fw = &sh_css_sp_fw;
- HIVE_ADDR_ia_css_isys_sp_error_cnt =
- fw->info.sp.perf_counter_input_system_error;
-
- (void)HIVE_ADDR_ia_css_isys_sp_error_cnt;
-
- sp_dmem_load(SP0_ID,
- (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt),
- &ia_css_sp_input_system_error_cnt,
- sizeof(ia_css_sp_input_system_error_cnt));
-
- for (i = 0; i < N_MIPI_PORT_ID + 1; i++) {
- ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n",
- i, ia_css_sp_input_system_error_cnt[i]);
- }
-}
-
/*
* @brief Initialize the debug mode.
* Refer to "ia_css_debug.h" for more details.
#endif
}
-/* Tagger state dump function. The tagger is only available when the CSS
- * contains an input system (2400 or 2401). */
-void ia_css_debug_tagger_state(void)
-{
- unsigned int i;
- unsigned int HIVE_ADDR_tagger_frames;
- ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER];
-
- HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr;
-
- /* This variable is not used in crun */
- (void)HIVE_ADDR_tagger_frames;
-
- /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */
- sp_dmem_load(SP0_ID,
- (unsigned int)sp_address_of(tagger_frames),
- tbuf_frames,
- sizeof(tbuf_frames));
-
- ia_css_debug_dtrace(2, "Tagger Info:\n");
- for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) {
- ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n",
- i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock);
- }
-}
-
/* ISP2401 */
void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps)
{
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