clk: samsung: exynos850: Add PDMA clocks

Add Peripheral DMA (PDMA) clocks in CMU_CORE controller:
  - PDMA_ACLK: clock for PDMA0 (regular DMA)
  - SPDMA_ACLK: clock for PDMA1 (secure DMA)

Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20240120012948.8836-4-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index bdc1eef7d6e548d81d15f7b007f0c1e36a45071e..01913dc4eb2751fcf7def91798d9bb4d60bfea4e 100644 (file)
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -26,7 +26,7 @@
 #define CLKS_NR_IS                     (CLK_GOUT_IS_SYSREG_PCLK + 1)
 #define CLKS_NR_MFCMSCL                        (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
 #define CLKS_NR_PERI                   (CLK_GOUT_WDT1_PCLK + 1)
-#define CLKS_NR_CORE                   (CLK_GOUT_SYSREG_CORE_PCLK + 1)
+#define CLKS_NR_CORE                   (CLK_GOUT_SPDMA_CORE_ACLK + 1)
 #define CLKS_NR_DPU                    (CLK_GOUT_DPU_SYSREG_PCLK + 1)
 
 /* ---- CMU_TOP ------------------------------------------------------------- */
@@ -1667,6 +1667,8 @@ CLK_OF_DECLARE(exynos850_cmu_peri, "samsung,exynos850-cmu-peri",
 #define CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK   0x2044
 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK  0x20e8
 #define CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN 0x20ec
+#define CLK_CON_GAT_GOUT_CORE_PDMA_ACLK                0x20f0
+#define CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK       0x2124
 #define CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK       0x2128
 #define CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK       0x212c
 #define CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK 0x2130
@@ -1683,6 +1685,8 @@ static const unsigned long core_clk_regs[] __initconst = {
        CLK_CON_GAT_GOUT_CORE_GPIO_CORE_PCLK,
        CLK_CON_GAT_GOUT_CORE_MMC_EMBD_I_ACLK,
        CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
+       CLK_CON_GAT_GOUT_CORE_PDMA_ACLK,
+       CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK,
        CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK,
        CLK_CON_GAT_GOUT_CORE_SSS_I_PCLK,
        CLK_CON_GAT_GOUT_CORE_SYSREG_CORE_PCLK,
@@ -1726,6 +1730,10 @@ static const struct samsung_gate_clock core_gate_clks[] __initconst = {
        GATE(CLK_GOUT_MMC_EMBD_SDCLKIN, "gout_mmc_embd_sdclkin",
             "mout_core_mmc_embd_user", CLK_CON_GAT_GOUT_CORE_MMC_EMBD_SDCLKIN,
             21, CLK_SET_RATE_PARENT, 0),
+       GATE(CLK_GOUT_PDMA_CORE_ACLK, "gout_pdma_core_aclk",
+            "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_PDMA_ACLK, 21, 0, 0),
+       GATE(CLK_GOUT_SPDMA_CORE_ACLK, "gout_spdma_core_aclk",
+            "mout_core_bus_user", CLK_CON_GAT_GOUT_CORE_SPDMA_ACLK, 21, 0, 0),
        GATE(CLK_GOUT_SSS_ACLK, "gout_sss_aclk", "mout_core_sss_user",
             CLK_CON_GAT_GOUT_CORE_SSS_I_ACLK, 21, 0, 0),
        GATE(CLK_GOUT_SSS_PCLK, "gout_sss_pclk", "dout_core_busp",