drm/xe/mocs: Determine MCR separately for primary/media GT in kunit test

Although MOCS registers became multicast in graphics version 12.50 on
the primary GT, this transition did not happen until version 20 on the
media GT.  Considering each GT independently is mostly important for
MTL/ARL where the Xe_LPM+ IP has non-MCR MOCS registers, even though
Xe_LPG IP has MCR registers.

Bspec: 67789, 71186
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240314195825.3226856-3-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/xe/tests/xe_mocs.c b/drivers/gpu/drm/xe/tests/xe_mocs.c
index 25dd93ff16062b7e9d8de9fa8f883a2044daef94..7fd99ba96a1208d0cfcd363ccb23d121e57e52f5 100644 (file)
--- a/drivers/gpu/drm/xe/tests/xe_mocs.c
+++ b/drivers/gpu/drm/xe/tests/xe_mocs.c
@@ -51,7 +51,7 @@ static void read_l3cc_table(struct xe_gt *gt,
 
        for (i = 0; i < info->n_entries; i++) {
                if (!(i & 1)) {
-                       if (GRAPHICS_VERx100(xe) >= 1250)
+                       if (regs_are_mcr(gt))
                                reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_LNCFCMOCS(i >> 1));
                        else
                                reg_val = xe_mmio_read32(gt, XELP_LNCFCMOCS(i >> 1));
@@ -91,7 +91,7 @@ static void read_mocs_table(struct xe_gt *gt,
        KUNIT_ASSERT_EQ_MSG(test, ret, 0, "Forcewake Failed.\n");
 
        for (i = 0; i < info->n_entries; i++) {
-               if (GRAPHICS_VERx100(xe) >= 1250)
+               if (regs_are_mcr(gt))
                        reg_val = xe_gt_mcr_unicast_read_any(gt, XEHP_GLOBAL_MOCS(i));
                else
                        reg_val = xe_mmio_read32(gt, XELP_GLOBAL_MOCS(i));

diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
index f56f630fa29d0e16497d77cb01f49341e7088609..35ccd4ac00d296d22785cf363e1e269de87bd637 100644 (file)
--- a/drivers/gpu/drm/xe/xe_mocs.c
+++ b/drivers/gpu/drm/xe/xe_mocs.c
@@ -466,6 +466,16 @@ static u32 get_entry_control(const struct xe_mocs_info *info,
        return info->table[info->unused_entries_index].control_value;
 }
 
+static bool regs_are_mcr(struct xe_gt *gt)
+{
+       struct xe_device *xe = gt_to_xe(gt);
+
+       if (xe_gt_is_media_type(gt))
+               return MEDIA_VER(xe) >= 20;
+       else
+               return GRAPHICS_VERx100(xe) >= 1250;
+}
+
 static void __init_mocs_table(struct xe_gt *gt,
                              const struct xe_mocs_info *info)
 {
@@ -485,7 +495,7 @@ static void __init_mocs_table(struct xe_gt *gt,
                mocs_dbg(&gt_to_xe(gt)->drm, "GLOB_MOCS[%d] 0x%x 0x%x\n", i,
                         XELP_GLOBAL_MOCS(i).addr, mocs);
 
-               if (GRAPHICS_VERx100(gt_to_xe(gt)) > 1250)
+               if (regs_are_mcr(gt))
                        xe_gt_mcr_multicast_write(gt, XEHP_GLOBAL_MOCS(i), mocs);
                else
                        xe_mmio_write32(gt, XELP_GLOBAL_MOCS(i), mocs);
@@ -525,7 +535,7 @@ static void init_l3cc_table(struct xe_gt *gt,
                mocs_dbg(&gt_to_xe(gt)->drm, "LNCFCMOCS[%d] 0x%x 0x%x\n", i,
                         XELP_LNCFCMOCS(i).addr, l3cc);
 
-               if (GRAPHICS_VERx100(gt_to_xe(gt)) >= 1250)
+               if (regs_are_mcr(gt))
                        xe_gt_mcr_multicast_write(gt, XEHP_LNCFCMOCS(i), l3cc);
                else
                        xe_mmio_write32(gt, XELP_LNCFCMOCS(i), l3cc);