iio: addac: ad74413r: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: fea251b6a5db ("iio: addac: add AD74413R driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <cosmin.tanislav@analog.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-41-jic23@kernel.org

diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c
index bc5a58f7f77417e0e5c471a5af9d5e03bf950d9a..899bcd83f40bc5551a1b4ac830ee91e3d1249a88 100644 (file)
--- a/drivers/iio/addac/ad74413r.c
+++ b/drivers/iio/addac/ad74413r.c
@@ -77,13 +77,13 @@ struct ad74413r_state {
        struct spi_transfer     adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
+        * DMA (thus cache coherency maintenance) may require the
         * transfer buffers to live in their own cache lines.
         */
        struct {
                u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
                s64 timestamp;
-       } adc_samples_buf ____cacheline_aligned;
+       } adc_samples_buf __aligned(IIO_DMA_MINALIGN);
 
        u8      adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
        u8      reg_tx_buf[AD74413R_FRAME_SIZE];