drm/xe/pat: Define PAT tables as static
authorMatt Roper <matthew.d.roper@intel.com>
Mon, 27 Mar 2023 17:58:24 +0000 (10:58 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:30:26 +0000 (18:30 -0500)
The tables are only used within this file; there's no reason for them
not to be static.

Reviewed-by: Nirmoy Das <nirmoy.das@intel.com>
Link: https://lore.kernel.org/r/20230327175824.2967914-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_pat.c

index b59b6a2347bbd52ef33ebcba793ede3e490c8d5e..c2faf0931649f316185e644085c3c0bf836227ee 100644 (file)
@@ -32,7 +32,7 @@
 #define TGL_PAT_WC                             REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 1)
 #define TGL_PAT_UC                             REG_FIELD_PREP(TGL_MEM_TYPE_MASK, 0)
 
-const u32 tgl_pat_table[] = {
+static const u32 tgl_pat_table[] = {
        [0] = TGL_PAT_WB,
        [1] = TGL_PAT_WC,
        [2] = TGL_PAT_WT,
@@ -43,7 +43,7 @@ const u32 tgl_pat_table[] = {
        [7] = TGL_PAT_WB,
 };
 
-const u32 pvc_pat_table[] = {
+static const u32 pvc_pat_table[] = {
        [0] = TGL_PAT_UC,
        [1] = TGL_PAT_WC,
        [2] = TGL_PAT_WT,
@@ -54,7 +54,7 @@ const u32 pvc_pat_table[] = {
        [7] = PVC_PAT_CLOS(2) | TGL_PAT_WB,
 };
 
-const u32 mtl_pat_table[] = {
+static const u32 mtl_pat_table[] = {
        [0] = MTL_PAT_0_WB,
        [1] = MTL_PAT_1_WT,
        [2] = MTL_PAT_3_UC,