drm/msm/dpu: inline _setup_intf_ops()

Inline the _setup_intf_ops() function, it makes it easier to handle
different conditions involving INTF configuration.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/555551/
Link: https://lore.kernel.org/r/20230904020454.2945667-5-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
index 5dcc83dd47ef1058dbc51e36423a609c34848676..bf7c6e1d3ea589c77ce33ebfb3db5db683c96c42 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c
@@ -527,35 +527,6 @@ static void dpu_hw_intf_program_intf_cmd_cfg(struct dpu_hw_intf *ctx,
        DPU_REG_WRITE(&ctx->hw, INTF_CONFIG2, intf_cfg2);
 }
 
-static void _setup_intf_ops(struct dpu_hw_intf_ops *ops,
-               unsigned long cap, const struct dpu_mdss_version *mdss_rev)
-{
-       ops->setup_timing_gen = dpu_hw_intf_setup_timing_engine;
-       ops->setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
-       ops->get_status = dpu_hw_intf_get_status;
-       ops->enable_timing = dpu_hw_intf_enable_timing_engine;
-       ops->get_line_count = dpu_hw_intf_get_line_count;
-       if (cap & BIT(DPU_INTF_INPUT_CTRL))
-               ops->bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
-       ops->setup_misr = dpu_hw_intf_setup_misr;
-       ops->collect_misr = dpu_hw_intf_collect_misr;
-
-       if (cap & BIT(DPU_INTF_TE)) {
-               ops->enable_tearcheck = dpu_hw_intf_enable_te;
-               ops->disable_tearcheck = dpu_hw_intf_disable_te;
-               ops->connect_external_te = dpu_hw_intf_connect_external_te;
-               ops->vsync_sel = dpu_hw_intf_vsync_sel;
-               ops->disable_autorefresh = dpu_hw_intf_disable_autorefresh;
-       }
-
-       /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but
-        * we can configure it for DPU 7.0+ since the wide bus and DSC flags
-        * would not be set for DPU < 7.0 anyways
-        */
-       if (mdss_rev->core_major_ver >= 7)
-               ops->program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
-}
-
 struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
                void __iomem *addr, const struct dpu_mdss_version *mdss_rev)
 {
@@ -578,7 +549,32 @@ struct dpu_hw_intf *dpu_hw_intf_init(const struct dpu_intf_cfg *cfg,
         */
        c->idx = cfg->id;
        c->cap = cfg;
-       _setup_intf_ops(&c->ops, c->cap->features, mdss_rev);
+
+       c->ops.setup_timing_gen = dpu_hw_intf_setup_timing_engine;
+       c->ops.setup_prg_fetch  = dpu_hw_intf_setup_prg_fetch;
+       c->ops.get_status = dpu_hw_intf_get_status;
+       c->ops.enable_timing = dpu_hw_intf_enable_timing_engine;
+       c->ops.get_line_count = dpu_hw_intf_get_line_count;
+       c->ops.setup_misr = dpu_hw_intf_setup_misr;
+       c->ops.collect_misr = dpu_hw_intf_collect_misr;
+
+       if (cfg->features & BIT(DPU_INTF_INPUT_CTRL))
+               c->ops.bind_pingpong_blk = dpu_hw_intf_bind_pingpong_blk;
+
+       if (cfg->features & BIT(DPU_INTF_TE)) {
+               c->ops.enable_tearcheck = dpu_hw_intf_enable_te;
+               c->ops.disable_tearcheck = dpu_hw_intf_disable_te;
+               c->ops.connect_external_te = dpu_hw_intf_connect_external_te;
+               c->ops.vsync_sel = dpu_hw_intf_vsync_sel;
+               c->ops.disable_autorefresh = dpu_hw_intf_disable_autorefresh;
+       }
+
+       /* Technically, INTF_CONFIG2 is present for DPU 5.0+, but
+        * we can configure it for DPU 7.0+ since the wide bus and DSC flags
+        * would not be set for DPU < 7.0 anyways
+        */
+       if (mdss_rev->core_major_ver >= 7)
+               c->ops.program_intf_cmd_cfg = dpu_hw_intf_program_intf_cmd_cfg;
 
        return c;
 }