drm/i915: Use GEN12_RPSTAT register for GT freq

On GEN12+ use GEN12_RPSTAT register to get actual resolved GT
freq. GEN12_RPSTAT does not require a forcewake and will return 0 freq if
GT is in RC6.

v2:
  - Fixed review comments(Ashutosh)
  - Added function intel_rps_read_rpstat_fw to read RPSTAT without
    forcewake, required especially for GEN6_RPSTAT1 (Ashutosh, Tvrtko)
v3:
  - Updated commit title and message for more clarity (Ashutosh)
  - Replaced intel_rps_read_rpstat with direct read to GEN12_RPSTAT1 in
    read_cagf (Ashutosh)
v4: Remove GEN12_CAGF_SHIFT and use REG_FIELD_GET (Rodrigo)

Cc: Don Hiatt <donhiatt@gmail.com>
Cc: Andi Shyti <andi.shyti@intel.com>
Signed-off-by: Don Hiatt <don.hiatt@intel.com>
Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
Signed-off-by: Ashutosh Dixit <ashutosh.dixit@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221114123348.3474216-3-badal.nilawar@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
index f70cf5159a04cae8a236d9237b44c1a9edf40d17..b4ffcb11c4fe93d2dd13ec853bf43ef1b21101b8 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
+++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
@@ -1545,6 +1545,7 @@
 
 #define GEN12_RPSTAT1                          _MMIO(0x1381b4)
 #define   GEN12_VOLTAGE_MASK                   REG_GENMASK(10, 0)
+#define   GEN12_CAGF_MASK                      REG_GENMASK(19, 11)
 
 #define GEN11_GT_INTR_DW(x)                    _MMIO(0x190018 + ((x) * 4))
 #define   GEN11_CSME                           (31)

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 8a505e10f4c05ffc68ee4487c7ea71a83e17606a..9909d1f0db6309c632d601f361768bdd6149cb9c 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -2074,12 +2074,34 @@ void intel_rps_sanitize(struct intel_rps *rps)
                rps_disable_interrupts(rps);
 }
 
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps)
+{
+       struct drm_i915_private *i915 = rps_to_i915(rps);
+       i915_reg_t rpstat;
+
+       rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+       return intel_uncore_read_fw(rps_to_gt(rps)->uncore, rpstat);
+}
+
+u32 intel_rps_read_rpstat(struct intel_rps *rps)
+{
+       struct drm_i915_private *i915 = rps_to_i915(rps);
+       i915_reg_t rpstat;
+
+       rpstat = (GRAPHICS_VER(i915) >= 12) ? GEN12_RPSTAT1 : GEN6_RPSTAT1;
+
+       return intel_uncore_read(rps_to_gt(rps)->uncore, rpstat);
+}
+
 u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat)
 {
        struct drm_i915_private *i915 = rps_to_i915(rps);
        u32 cagf;
 
-       if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+       if (GRAPHICS_VER(i915) >= 12)
+               cagf = REG_FIELD_GET(GEN12_CAGF_MASK, rpstat);
+       else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
                cagf = REG_FIELD_GET(RPE_MASK, rpstat);
        else if (GRAPHICS_VER(i915) >= 9)
                cagf = REG_FIELD_GET(GEN9_CAGF_MASK, rpstat);
@@ -2099,7 +2121,9 @@ static u32 read_cagf(struct intel_rps *rps)
        struct intel_uncore *uncore = rps_to_uncore(rps);
        u32 freq;
 
-       if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+       if (GRAPHICS_VER(i915) >= 12) {
+               freq = intel_uncore_read(uncore, GEN12_RPSTAT1);
+       } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
                vlv_punit_get(i915);
                freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
                vlv_punit_put(i915);
@@ -2265,7 +2289,7 @@ static void rps_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
        rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
        rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
 
-       rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+       rpstat = intel_rps_read_rpstat(rps);
        rpcurupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
        rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
        rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
@@ -2400,7 +2424,7 @@ static void slpc_frequency_dump(struct intel_rps *rps, struct drm_printer *p)
        drm_printf(p, "PM MASK=0x%08x\n", pm_mask);
        drm_printf(p, "pm_intrmsk_mbz: 0x%08x\n",
                   rps->pm_intrmsk_mbz);
-       drm_printf(p, "RPSTAT1: 0x%08x\n", intel_uncore_read(uncore, GEN6_RPSTAT1));
+       drm_printf(p, "RPSTAT1: 0x%08x\n", intel_rps_read_rpstat(rps));
        drm_printf(p, "RPNSWREQ: %dMHz\n", intel_rps_get_requested_frequency(rps));
        drm_printf(p, "Lowest (RPN) frequency: %dMHz\n",
                   intel_gpu_freq(rps, caps.min_freq));

diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 110300dfd4383e85f8a3ab78b0341a528d74b211..9e1cad9ba0e9cbb77128e833e7afa1ef206f52fb 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -48,6 +48,8 @@ u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);
 u32 intel_rps_get_rpn_frequency(struct intel_rps *rps);
 u32 intel_rps_read_punit_req(struct intel_rps *rps);
 u32 intel_rps_read_punit_req_frequency(struct intel_rps *rps);
+u32 intel_rps_read_rpstat(struct intel_rps *rps);
+u32 intel_rps_read_rpstat_fw(struct intel_rps *rps);
 void gen6_rps_get_freq_caps(struct intel_rps *rps, struct intel_rps_freq_caps *caps);
 void intel_rps_raise_unslice(struct intel_rps *rps);
 void intel_rps_lower_unslice(struct intel_rps *rps);

diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c
index 958b37123bf12bc9a5f96d09c24d6a81574dc0ad..67140a87182f857f849044e38ff06ae9569c748c 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pmu.c
+++ b/drivers/gpu/drm/i915/i915_pmu.c
@@ -371,7 +371,6 @@ static void
 frequency_sample(struct intel_gt *gt, unsigned int period_ns)
 {
        struct drm_i915_private *i915 = gt->i915;
-       struct intel_uncore *uncore = gt->uncore;
        struct i915_pmu *pmu = &i915->pmu;
        struct intel_rps *rps = &gt->rps;
 
@@ -394,7 +393,7 @@ frequency_sample(struct intel_gt *gt, unsigned int period_ns)
                 * case we assume the system is running at the intended
                 * frequency. Fortunately, the read should rarely fail!
                 */
-               val = intel_uncore_read_fw(uncore, GEN6_RPSTAT1);
+               val = intel_rps_read_rpstat_fw(rps);
                if (val)
                        val = intel_rps_get_cagf(rps, val);
                else