drm/amdgpu: Modify .ras_fini function pointer parameter
authoryipechai <YiPeng.Chai@amd.com>
Thu, 17 Feb 2022 06:52:20 +0000 (14:52 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 2 Mar 2022 23:40:05 +0000 (18:40 -0500)
Modify .ras_fini function pointer parameter so that
we can remove redundant intermediate calls in some
ras blocks.

Signed-off-by: yipechai <YiPeng.Chai@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
19 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h
drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.c
drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.h
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.c
drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.h
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c
drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
drivers/gpu/drm/amd/amdgpu/amdgpu_ras.h
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.h
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.c
drivers/gpu/drm/amd/amdgpu/amdgpu_umc.h
drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
drivers/gpu/drm/amd/amdgpu/mca_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
drivers/gpu/drm/amd/amdgpu/soc15.c

index 52912b6bcb20d23bda52c74aa978b5c6b87d6f59..d020c459943337630b827cecff9c099723c0c877 100644 (file)
@@ -644,7 +644,7 @@ late_fini:
        return r;
 }
 
-void amdgpu_gfx_ras_fini(struct amdgpu_device *adev)
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__GFX) &&
                        adev->gfx.ras_if)
index ccca0a85b982ba3929bcb675db7b2c6c36ce8cbb..f7c50ab4589c7595ccab2810b099f4ea5a5db31b 100644 (file)
@@ -387,7 +387,7 @@ bool amdgpu_gfx_is_me_queue_enabled(struct amdgpu_device *adev, int me,
 void amdgpu_gfx_off_ctrl(struct amdgpu_device *adev, bool enable);
 int amdgpu_get_gfx_off_status(struct amdgpu_device *adev, uint32_t *value);
 int amdgpu_gfx_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-void amdgpu_gfx_ras_fini(struct amdgpu_device *adev);
+void amdgpu_gfx_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 int amdgpu_gfx_process_ras_data_cb(struct amdgpu_device *adev,
                void *err_data,
                struct amdgpu_iv_entry *entry);
index 78498d1d17697e08745482969520c8b536d72fca..350fbfec1e037b54cdf49402be147815d5f81c29 100644 (file)
@@ -455,16 +455,16 @@ int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev)
 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev)
 {
        if (adev->umc.ras && adev->umc.ras->ras_block.ras_fini)
-               adev->umc.ras->ras_block.ras_fini(adev);
+               adev->umc.ras->ras_block.ras_fini(adev, NULL);
 
        if (adev->mmhub.ras && adev->mmhub.ras->ras_block.ras_fini)
-               adev->mmhub.ras->ras_block.ras_fini(adev);
+               adev->mmhub.ras->ras_block.ras_fini(adev, NULL);
 
        if (adev->gmc.xgmi.ras && adev->gmc.xgmi.ras->ras_block.ras_fini)
-               adev->gmc.xgmi.ras->ras_block.ras_fini(adev);
+               adev->gmc.xgmi.ras->ras_block.ras_fini(adev, NULL);
 
        if (adev->hdp.ras && adev->hdp.ras->ras_block.ras_fini)
-               adev->hdp.ras->ras_block.ras_fini(adev);
+               adev->hdp.ras->ras_block.ras_fini(adev, NULL);
 }
 
        /*
index b7fbc114a17592ddb85057afd45941549b48c575..0f224e21cd5556603201669d8d64e9172ace4f6b 100644 (file)
@@ -24,7 +24,7 @@
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
 
-void amdgpu_hdp_ras_fini(struct amdgpu_device *adev)
+void amdgpu_hdp_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP) &&
            adev->hdp.ras_if)
index aabd59aa5213b11c0ad6cd245defaf0d27166454..c05cd992ef8a552c5ead34ac770b1d3e97e7f420 100644 (file)
@@ -44,5 +44,5 @@ struct amdgpu_hdp {
 };
 
 int amdgpu_hdp_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-void amdgpu_hdp_ras_fini(struct amdgpu_device *adev);
+void amdgpu_hdp_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 #endif /* __AMDGPU_HDP_H__ */
index 42413813765adbc2f62267623155ea646aaaa41c..6dfcedcc37fd3816a6bf7321415af489f69b9210 100644 (file)
@@ -24,7 +24,7 @@
 #include "amdgpu.h"
 #include "amdgpu_ras.h"
 
-void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev)
+void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB) &&
                        adev->mmhub.ras_if)
index 240b26d9a388e2807d8ba16fb99cab05359f4089..253f047379cfadc5e611076c21e13c4191e62ad7 100644 (file)
@@ -47,6 +47,6 @@ struct amdgpu_mmhub {
        struct amdgpu_mmhub_ras  *ras;
 };
 
-void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev);
+void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 #endif
 
index f09ad80f077263ce722cbab76d31c82a8c265b2a..0de2fdf31eed7918f402350d0f04846b5dbd7991 100644 (file)
@@ -44,7 +44,7 @@ late_fini:
        return r;
 }
 
-void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)
+void amdgpu_nbio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&
                        adev->nbio.ras_if)
index f9546c7341b80b428d675d8511aadaa5c349aecb..3222e1cae13436a201737d29716aaca5cff80fc9 100644 (file)
@@ -105,5 +105,5 @@ struct amdgpu_nbio {
 };
 
 int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-void amdgpu_nbio_ras_fini(struct amdgpu_device *adev);
+void amdgpu_nbio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 #endif
index 143a83043d7c2ee0804a2dc95fc10967834a150b..7cddaad90d6d971b1d8736f0b73c04563bcc346a 100644 (file)
@@ -491,7 +491,7 @@ struct amdgpu_ras_block_object {
        int (*ras_block_match)(struct amdgpu_ras_block_object *block_obj,
                                enum amdgpu_ras_block block, uint32_t sub_block_index);
        int (*ras_late_init)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-       void (*ras_fini)(struct amdgpu_device *adev);
+       void (*ras_fini)(struct amdgpu_device *adev, struct ras_common_if *ras_block);
        ras_ih_cb ras_cb;
        const struct amdgpu_ras_block_hw_ops *hw_ops;
 };
index 3b5c43575aa3e98697b8442b0174854b00709815..863035a94bd86e1ca738ee8b37a05e486ecbef01 100644 (file)
@@ -111,7 +111,7 @@ late_fini:
        return r;
 }
 
-void amdgpu_sdma_ras_fini(struct amdgpu_device *adev)
+void amdgpu_sdma_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__SDMA) &&
                        adev->sdma.ras_if)
index 8b226ffee32c018a9743f868005791af1ee18eed..34ec60dfe5e8ff7a8daf8241c5e64e44aee55a6d 100644 (file)
@@ -118,7 +118,7 @@ int amdgpu_sdma_get_index_from_ring(struct amdgpu_ring *ring, uint32_t *index);
 uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring, unsigned vmid);
 int amdgpu_sdma_ras_late_init(struct amdgpu_device *adev,
                              struct ras_common_if *ras_block);
-void amdgpu_sdma_ras_fini(struct amdgpu_device *adev);
+void amdgpu_sdma_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 int amdgpu_sdma_process_ras_data_cb(struct amdgpu_device *adev,
                void *err_data,
                struct amdgpu_iv_entry *entry);
index 9400260e3263e24264ec29268604d2ce6a0c9561..41e976733c57627731e99dab567838f4c47c8796 100644 (file)
@@ -162,7 +162,7 @@ late_fini:
        return r;
 }
 
-void amdgpu_umc_ras_fini(struct amdgpu_device *adev)
+void amdgpu_umc_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC) &&
                        adev->umc.ras_if)
index e4b3678a6685c95e66025e984842f164ab6f0f15..c8deba8dacb59d944da4bd29ac6ae32842492eba 100644 (file)
@@ -73,7 +73,7 @@ struct amdgpu_umc {
 };
 
 int amdgpu_umc_ras_late_init(struct amdgpu_device *adev, struct ras_common_if *ras_block);
-void amdgpu_umc_ras_fini(struct amdgpu_device *adev);
+void amdgpu_umc_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block);
 int amdgpu_umc_poison_handler(struct amdgpu_device *adev,
                void *ras_error_status,
                bool reset);
index 91817a31f3e1297e6faee9653f751e67ffaf9686..3e56adea84a359208d62c70b1ba78557a064cc6e 100644 (file)
@@ -768,7 +768,7 @@ static int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev, struct ras_comm
        return amdgpu_ras_block_late_init(adev, ras_block);
 }
 
-static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev)
+static void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__XGMI_WAFL) &&
                        adev->gmc.xgmi.ras_if)
index 1997f129db9c64c5df71b22b3aeb58c1ac7072be..3ecb238c64831d3b6f5aa80c3c5df1863b892141 100644 (file)
@@ -2433,7 +2433,7 @@ static int gfx_v9_0_sw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        if (adev->gfx.ras && adev->gfx.ras->ras_block.ras_fini)
-               adev->gfx.ras->ras_block.ras_fini(adev);
+               adev->gfx.ras->ras_block.ras_fini(adev, NULL);
 
        for (i = 0; i < adev->gfx.num_gfx_rings; i++)
                amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
index b4b36899f5c6ac9ffe5fa7b87135c2a85631aac1..02c50be19d3b684851c1df44eeeaa9033d8a188e 100644 (file)
@@ -37,7 +37,7 @@ static void mca_v3_0_mp0_query_ras_error_count(struct amdgpu_device *adev,
                                         ras_error_status);
 }
 
-static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev)
+static void mca_v3_0_mp0_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        amdgpu_mca_ras_fini(adev, &adev->mca.mp0);
 }
@@ -83,7 +83,7 @@ static void mca_v3_0_mp1_query_ras_error_count(struct amdgpu_device *adev,
                                         ras_error_status);
 }
 
-static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev)
+static void mca_v3_0_mp1_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        amdgpu_mca_ras_fini(adev, &adev->mca.mp1);
 }
@@ -115,7 +115,7 @@ static void mca_v3_0_mpio_query_ras_error_count(struct amdgpu_device *adev,
                                         ras_error_status);
 }
 
-static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev)
+static void mca_v3_0_mpio_ras_fini(struct amdgpu_device *adev, struct ras_common_if *ras_block)
 {
        amdgpu_mca_ras_fini(adev, &adev->mca.mpio);
 }
index e26c39fcd3363485702f192b9e96759d241f540a..d0a9012e53d7c301982f7bdf88a41ef54dbe4c7f 100644 (file)
@@ -1997,7 +1997,7 @@ static int sdma_v4_0_sw_fini(void *handle)
 
        if (adev->sdma.ras && adev->sdma.ras->ras_block.hw_ops &&
                adev->sdma.ras->ras_block.ras_fini)
-               adev->sdma.ras->ras_block.ras_fini(adev);
+               adev->sdma.ras->ras_block.ras_fini(adev, NULL);
 
        for (i = 0; i < adev->sdma.num_instances; i++) {
                amdgpu_ring_fini(&adev->sdma.instance[i].ring);
index b7c24149a6bd3fab58527a10d0ab8eea5d16bbca..34cd5cad7da5a1a1b35fdaec3b41874dcf0a15df 100644 (file)
@@ -1215,7 +1215,7 @@ static int soc15_common_sw_fini(void *handle)
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
        if (adev->nbio.ras && adev->nbio.ras->ras_block.ras_fini)
-               adev->nbio.ras->ras_block.ras_fini(adev);
+               adev->nbio.ras->ras_block.ras_fini(adev, NULL);
 
        if (adev->df.funcs &&
            adev->df.funcs->sw_fini)