#include <linux/errno.h>
 #include <linux/err.h>
 #include <linux/qcom_scm.h>
+#include <linux/arm-smccc.h>
 #include <linux/dma-mapping.h>
 
 #include "qcom_scm.h"
 static u32 __scm_legacy_do(u32 cmd_addr)
 {
        int context_id;
-       register u32 r0 asm("r0") = 1;
-       register u32 r1 asm("r1") = (u32)&context_id;
-       register u32 r2 asm("r2") = cmd_addr;
+       struct arm_smccc_res res;
        do {
-               asm volatile(
-                       __asmeq("%0", "r0")
-                       __asmeq("%1", "r0")
-                       __asmeq("%2", "r1")
-                       __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
-                       ".arch_extension sec\n"
-#endif
-                       "smc    #0      @ switch to secure world\n"
-                       : "=r" (r0)
-                       : "r" (r0), "r" (r1), "r" (r2)
-                       : "r3", "r12");
-       } while (r0 == QCOM_SCM_INTERRUPTED);
-
-       return r0;
+               arm_smccc_smc(1, (unsigned long)&context_id, cmd_addr,
+                             0, 0, 0, 0, 0, &res);
+       } while (res.a0 == QCOM_SCM_INTERRUPTED);
+
+       return res.a0;
 }
 
 /**
 static s32 qcom_scm_call_atomic1(u32 svc, u32 cmd, u32 arg1)
 {
        int context_id;
+       struct arm_smccc_res res;
+
+       arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 1),
+                     (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
 
-       register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 1);
-       register u32 r1 asm("r1") = (u32)&context_id;
-       register u32 r2 asm("r2") = arg1;
-
-       asm volatile(
-                       __asmeq("%0", "r0")
-                       __asmeq("%1", "r0")
-                       __asmeq("%2", "r1")
-                       __asmeq("%3", "r2")
-#ifdef REQUIRES_SEC
-                       ".arch_extension sec\n"
-#endif
-                       "smc    #0      @ switch to secure world\n"
-                       : "=r" (r0)
-                       : "r" (r0), "r" (r1), "r" (r2)
-                       : "r3", "r12");
-       return r0;
+       return res.a0;
 }
 
 /**
 static s32 qcom_scm_call_atomic2(u32 svc, u32 cmd, u32 arg1, u32 arg2)
 {
        int context_id;
+       struct arm_smccc_res res;
+
+       arm_smccc_smc(SCM_LEGACY_ATOMIC_ID(svc, cmd, 2),
+                     (unsigned long)&context_id, arg1, 0, 0, 0, 0, 0, &res);
 
-       register u32 r0 asm("r0") = SCM_LEGACY_ATOMIC_ID(svc, cmd, 2);
-       register u32 r1 asm("r1") = (u32)&context_id;
-       register u32 r2 asm("r2") = arg1;
-       register u32 r3 asm("r3") = arg2;
-
-       asm volatile(
-                       __asmeq("%0", "r0")
-                       __asmeq("%1", "r0")
-                       __asmeq("%2", "r1")
-                       __asmeq("%3", "r2")
-                       __asmeq("%4", "r3")
-#ifdef REQUIRES_SEC
-                       ".arch_extension sec\n"
-#endif
-                       "smc    #0      @ switch to secure world\n"
-                       : "=r" (r0)
-                       : "r" (r0), "r" (r1), "r" (r2), "r" (r3)
-                       : "r12");
-       return r0;
+       return res.a0;
 }
 
 /**