arm64: dts: ti: k3-j721s2-main: Enable crypto accelerator
authorJayesh Choudhary <j-choudhary@ti.com>
Mon, 31 Oct 2022 20:06:33 +0000 (01:36 +0530)
committerNishanth Menon <nm@ti.com>
Thu, 17 Nov 2022 03:11:12 +0000 (21:11 -0600)
Add the node for SA2UL for supporting hardware crypto algorithms,
including SHA1, SHA256, SHA512, AES, 3DES and AEAD suites.
Add rng node for hardware random number generator.

Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Manorit Chawdhry <m-chawdhry@ti.com>
Acked-by: Matt Ranostay <mranostay@ti.com>
Acked-by: Andrew Davis <afd@ti.com>
Link: https://lore.kernel.org/r/20221031200633.26997-1-j-choudhary@ti.com
arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi

index 7ccf8a761fc9ffd76985a80d6c959e7b58410b11..8915132efcc1b7edb6ad5ac5d734f8463ffcc130 100644 (file)
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
+       main_crypto: crypto@4e00000 {
+               compatible = "ti,j721e-sa2ul";
+               reg = <0x00 0x04e00000 0x00 0x1200>;
+               power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>;
+               #address-cells = <2>;
+               #size-cells = <2>;
+               ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;
+
+               dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
+                      <&main_udmap 0x4a41>;
+               dma-names = "tx", "rx1", "rx2";
+
+               rng: rng@4e10000 {
+                       compatible = "inside-secure,safexcel-eip76";
+                       reg = <0x00 0x04e10000 0x00 0x7d>;
+                       interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
+               };
+       };
+
        main_uart0: serial@2800000 {
                compatible = "ti,j721e-uart", "ti,am654-uart";
                reg = <0x00 0x02800000 0x00 0x200>;