arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy"

Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed in [1].
Re-name subnodes of serdes in J721E to 'phy'.

[1] -> http://lore.kernel.org/r/20200909203631.GA3026331@bogus

Fixes: 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board: Configure the PCIe instances")
Fixes: 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed support for USB0")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Reviewed-by: Aswath Govindraju <a-govindraju@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Link: https://lore.kernel.org/r/20210603143427.28735-5-kishon@ti.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
index 8e7e013f9fffea00e9ecc708e6cc15a0c6c8a89b..8bd02d9e28ad3ce30004b26de70433685ce4f639 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
@@ -359,7 +359,7 @@
 };
 
 &serdes3 {
-       serdes3_usb_link: link@0 {
+       serdes3_usb_link: phy@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;
@@ -674,7 +674,7 @@
        assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
        assigned-clock-parents = <&wiz0_pll1_refclk>;
 
-       serdes0_pcie_link: link@0 {
+       serdes0_pcie_link: phy@0 {
                reg = <0>;
                cdns,num-lanes = <1>;
                #phy-cells = <0>;
@@ -687,7 +687,7 @@
        assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
        assigned-clock-parents = <&wiz1_pll1_refclk>;
 
-       serdes1_pcie_link: link@0 {
+       serdes1_pcie_link: phy@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;
@@ -700,7 +700,7 @@
        assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
        assigned-clock-parents = <&wiz2_pll1_refclk>;
 
-       serdes2_pcie_link: link@0 {
+       serdes2_pcie_link: phy@0 {
                reg = <0>;
                cdns,num-lanes = <2>;
                #phy-cells = <0>;